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Commit 587764ea authored by Hareesh Gundu's avatar Hareesh Gundu
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msm: kgsl: Add GBIF L2 CGC control with A6x CGC 



GBIF L2 CGC is not covered in UCHE CGC control.
Hence handle GBIF L2 CGC settings separately.

Change-Id: I9f33b2a868a81a68c5957990f737a3eeab7cd6fc
Signed-off-by: default avatarHareesh Gundu <hareeshg@codeaurora.org>
parent 73db1046

drivers/gpu/msm/adreno_a6xx.c

+4 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ static u32 a6xx_pwrup_reglist[] = { 
	A6XX_SP_NC_MODE_CNTL,

	A6XX_PC_DBG_ECO_CNTL,

	A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE,

	A6XX_UCHE_GBIF_GX_CONFIG,

};



/* IFPC only static powerup restore list */
@@ -372,6 +373,9 @@ static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on) 
		kgsl_regwrite(device, a6xx_core->hwcg[i].offset,

			on ? a6xx_core->hwcg[i].value : 0);



	/* GBIF L2 CGC control is not part of the UCHE */

	kgsl_regrmw(device, A6XX_UCHE_GBIF_GX_CONFIG, 0x70000, on ? 2 : 0);



	/*

	 * Enable SP clock after programming HWCG registers.

	 * A612 and A610 GPU is not having the GX power domain.