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Commit 067c878a authored by Yongqiang Sun's avatar Yongqiang Sun Committed by Alex Deucher
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drm/amd/display: Fixed switching mode half screen gamma incorrect. 



	Half screen gamma setting and cursor are incorrect
	when switching mode through win+p due to wrong programming
	gamma sequence (In case of bottom pipe, gamma and cursor are
	programmed before front end programmed, pipe is power gated).

	change:
	1. Cache curor attributes to stream
	2. Move set gamma and cursor inside front end
	   programming.

Signed-off-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d050f8ed

drivers/gpu/drm/amd/display/dc/core/dc.c

+0 −15
Original line number Diff line number Diff line
@@ -1269,10 +1269,6 @@ static void commit_planes_for_stream(struct dc *dc, 
	/* Full fe update*/

	for (j = 0; j < dc->res_pool->pipe_count; j++) {

		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

		struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[j];

		bool is_new_pipe_surface = cur_pipe_ctx->plane_state != pipe_ctx->plane_state;

		struct dc_cursor_position position = { 0 };





		if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->plane_state)

			continue;
@@ -1283,17 +1279,6 @@ static void commit_planes_for_stream(struct dc *dc, 
			dc->hwss.apply_ctx_for_surface(

					dc, pipe_ctx->stream, stream_status->plane_count, context);

		}



		/* TODO: this is a hack w/a for switching from mpo to pipe split */

		dc_stream_set_cursor_position(pipe_ctx->stream, &position);



		if (is_new_pipe_surface) {

			dc->hwss.update_plane_addr(dc, pipe_ctx);

			dc->hwss.set_input_transfer_func(

					pipe_ctx, pipe_ctx->plane_state);

			dc->hwss.set_output_transfer_func(

					pipe_ctx, pipe_ctx->stream);

		}

	}



	if (update_type > UPDATE_TYPE_FAST)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

+8 −1
Original line number Diff line number Diff line
@@ -173,7 +173,7 @@ struct dc_stream_status *dc_stream_get_status( 
 * Update the cursor attributes and set cursor surface address

 */

bool dc_stream_set_cursor_attributes(

	const struct dc_stream_state *stream,

	struct dc_stream_state *stream,

	const struct dc_cursor_attributes *attributes)

{

	int i;
@@ -189,6 +189,11 @@ bool dc_stream_set_cursor_attributes( 
			return false;

	}



	if (attributes->address.quad_part == 0) {

		dm_error("DC: Cursor address is 0!\n");

		return false;

	}



	core_dc = stream->ctx->dc;

	res_ctx = &core_dc->current_state->res_ctx;
@@ -214,6 +219,8 @@ bool dc_stream_set_cursor_attributes( 
				pipe_ctx->plane_res.xfm, attributes);

	}



	stream->cursor_attributes = *attributes;



	return true;

}

drivers/gpu/drm/amd/display/dc/dc.h

+3 −1
Original line number Diff line number Diff line
@@ -574,6 +574,8 @@ struct dc_stream_state { 


	struct dc_stream_status status;



	struct dc_cursor_attributes cursor_attributes;



	/* from stream struct */

	struct kref refcount;

};
@@ -1013,7 +1015,7 @@ struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 
 ******************************************************************************/

/* TODO: Deprecated once we switch to dc_set_cursor_position */

bool dc_stream_set_cursor_attributes(

	const struct dc_stream_state *stream,

	struct dc_stream_state *stream,

	const struct dc_cursor_attributes *attributes);



bool dc_stream_set_cursor_position(

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+10 −0
Original line number Diff line number Diff line
@@ -2725,6 +2725,8 @@ static void dce110_program_front_end_for_pipe( 
	struct dc_plane_state *plane_state = pipe_ctx->plane_state;

	struct xfm_grph_csc_adjustment adjust;

	struct out_csc_color_matrix tbl_entry;

	struct pipe_ctx *cur_pipe_ctx =

					&dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

	unsigned int i;



	memset(&tbl_entry, 0, sizeof(tbl_entry));
@@ -2815,6 +2817,14 @@ static void dce110_program_front_end_for_pipe( 
				&plane_state->tiling_info,

				plane_state->rotation);



	/* Moved programming gamma from dc to hwss */

	if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {

		dc->hwss.set_input_transfer_func(

				pipe_ctx, pipe_ctx->plane_state);

		dc->hwss.set_output_transfer_func(

				pipe_ctx, pipe_ctx->stream);

	}



	dm_logger_write(dc->ctx->logger, LOG_SURFACE,

			"Pipe:%d 0x%x: addr hi:0x%x, "

			"addr low:0x%x, "

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+17 −0
Original line number Diff line number Diff line
@@ -2408,6 +2408,10 @@ static void program_all_pipe_in_tree( 
	}



	if (pipe_ctx->plane_state != NULL) {

		struct dc_cursor_position position = { 0 };

		struct pipe_ctx *cur_pipe_ctx =

				&dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];



		dcn10_power_on_fe(dc, pipe_ctx, context);



		/* temporary dcn1 wa:
@@ -2422,6 +2426,19 @@ static void program_all_pipe_in_tree( 
		toggle_watermark_change_req(dc->hwseq);



		update_dchubp_dpp(dc, pipe_ctx, context);



		/* TODO: this is a hack w/a for switching from mpo to pipe split */

		dc_stream_set_cursor_position(pipe_ctx->stream, &position);



		dc_stream_set_cursor_attributes(pipe_ctx->stream,

				&pipe_ctx->stream->cursor_attributes);



		if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {

			dc->hwss.set_input_transfer_func(

					pipe_ctx, pipe_ctx->plane_state);

			dc->hwss.set_output_transfer_func(

					pipe_ctx, pipe_ctx->stream);

		}

	}



	if (dc->debug.sanity_checks) {