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Commit d050f8ed authored by Hersen Wu's avatar Hersen Wu Committed by Alex Deucher
Browse files

drm/amd/display: add dpms state to DC 



- avoid eDP screen flash 4 times when resume from s3
- improve s3 and boot time

Signed-off-by: default avatarHersen Wu <hersenxs.wu@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8e7095b9

drivers/gpu/drm/amd/display/dc/core/dc.c

+38 −1
Original line number Diff line number Diff line
@@ -332,7 +332,16 @@ static void set_dither_option(struct dc_stream_state *stream, 
{

	struct bit_depth_reduction_params params;

	struct dc_link *link = stream->status.link;

	struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

	struct pipe_ctx *pipes;

	int i;



	for (i = 0; i < MAX_PIPES; i++) {

		if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==

				stream) {

			pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];

			break;

		}

	}



	memset(&params, 0, sizeof(params));

	if (!stream)
@@ -349,6 +358,31 @@ static void set_dither_option(struct dc_stream_state *stream, 
		opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);

}



void set_dpms(

	struct dc *dc,

	struct dc_stream_state *stream,

	bool dpms_off)

{

	struct pipe_ctx *pipe_ctx;

	int i;



	for (i = 0; i < MAX_PIPES; i++) {

		if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {

			pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

			break;

		}

	}



	if (stream->dpms_off != dpms_off) {

		stream->dpms_off = dpms_off;

		if (dpms_off)

			core_link_disable_stream(pipe_ctx,

					KEEP_ACQUIRED_RESOURCE);

		else

			core_link_enable_stream(dc->current_state, pipe_ctx);

	}

}



static void allocate_dc_stream_funcs(struct dc  *dc)

{

	if (dc->hwss.set_drr != NULL) {
@@ -371,6 +405,9 @@ static void allocate_dc_stream_funcs(struct dc *dc) 
	dc->stream_funcs.set_dither_option =

			set_dither_option;



	dc->stream_funcs.set_dpms =

			set_dpms;



	dc->link_funcs.set_drive_settings =

			set_drive_settings;

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+4 −0
Original line number Diff line number Diff line
@@ -2321,6 +2321,10 @@ void core_link_enable_stream( 


	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

		allocate_mst_payload(pipe_ctx);



	if (dc_is_dp_signal(pipe_ctx->stream->signal))

		core_dc->hwss.unblank_stream(pipe_ctx,

			&pipe_ctx->stream->sink->link->cur_link_settings);

}



void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)

drivers/gpu/drm/amd/display/dc/dc.h

+5 −0
Original line number Diff line number Diff line
@@ -133,6 +133,10 @@ struct dc_stream_state_funcs { 


	void (*set_dither_option)(struct dc_stream_state *stream,

			enum dc_dither_option option);



	void (*set_dpms)(struct dc *dc,

			struct dc_stream_state *stream,

			bool dpms_off);

};



struct link_training_settings;
@@ -566,6 +570,7 @@ struct dc_stream_state { 


	int phy_pix_clk;

	enum signal_type signal;

	bool dpms_off;



	struct dc_stream_status status;

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+6 −7
Original line number Diff line number Diff line
@@ -1364,12 +1364,8 @@ static enum dc_status apply_single_controller_ctx_to_hw( 
	resource_build_info_frame(pipe_ctx);

	dce110_update_info_frame(pipe_ctx);

	if (!pipe_ctx_old->stream) {

		if (!pipe_ctx->stream->dpms_off)

			core_link_enable_stream(context, pipe_ctx);





		if (dc_is_dp_signal(pipe_ctx->stream->signal))

			dce110_unblank_stream(pipe_ctx,

				&stream->sink->link->cur_link_settings);

	}



	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
@@ -1879,7 +1875,10 @@ static void dce110_reset_hw_ctx_wrap( 
				pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

			struct clock_source *old_clk = pipe_ctx_old->clock_source;



			/* disable already, no need to disable again */

			if (!pipe_ctx->stream->dpms_off)

				core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);



			pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);

			if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {

				dm_error("DC: failed to blank crtc!\n");

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+5 −6
Original line number Diff line number Diff line
@@ -1037,12 +1037,11 @@ static void reset_back_end_for_pipe( 
		return;

	}



	/* TODOFPGA break core_link_disable_stream into 2 functions:

	 * disable_stream and disable_link. disable_link will disable PHYPLL

	 * which is used by otg. Move disable_link after disable_crtc

	 */

	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))

	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

		/* DPMS may already disable */

		if (!pipe_ctx->stream->dpms_off)

			core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);

	}



	/* by upper caller loop, parent pipe: pipe0, will be reset last.

	 * back end share by all pipes and will be disable only when disable