Merge "dt-bindings: arm: msm: Introduce qsee_ipc_irq_bridge bindings"

Binding for the QTI Secure Execution Environment IRQ controller

===============================================================

The QTI Secure Execution Environment (QSEE) IRQ controller facilitates receiving

and clearing interrupts from QSEE. Each interrupt from QSEE has a set of control

registers to mask, clear and get the status of interrupts. This controller will

create an interrupt for clients to register with based on the bits available in

the control registers.

- compatible:

	Usage: required

	Value type: <string>

	Definition: must be one of:

		    "qcom,sm8150-qsee-irq",

		    "qcom,kona-qsee-irq"

- syscon:

	usage: required

	Value type: <prop-encoded-array>

	Definition: phandle to a syscon node representing the scsr registers

- interrupts:

	Usage: required

	Value type: <prop-encoded array>

	Definition: multiple entries specifying the interrupts from QSEE

- interrupt-names:

	Usage: required

	Value type: <string>

	Definition: Interrupt names should be one of the following to map the

		    interrupt back to the correct registers.

		    - sp_ipc%d

		    - sp_rmb

- interrupt-controller:

	Usage: required

	Value type: <empty>

	Definition: Identifies this node as an interrupt controller

- #interrupt-cells

	Usage: required

	Value type: <u32>

	Definition: must be 3 - for interrupts to encode these properties:

		    - u32 denoting index of desired interrupt in @interrupts

		    - u32 denoting bit of interrupt bank

		    - u32 denoting IRQ flags

= EXAMPLE

The following example shows the QSEE_IRQ setup with the GLINK SPSS node, defined

from the sm8150 apps processor's point-of-view. In this example the GLINK node

registers for the sp_ipc0 interrupt(index 0 in interrupt-names) and the 0th

bit on the sp_ipc0 interrupt bank.

sp_scsr_block: syscon@1880000 {

	compatible = “syscon”;

	reg = <0x1880000 0x10000>;

};

intsp: qcom,qsee_irq {

	compatible = "qcom,sm8150-qsee-irq";

	syscon = <&sp_scsr_block>;

	interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>,

		     <0 349 IRQ_TYPE_LEVEL_HIGH>;

	interrupt-names = "sp_ipc0",

			  "sp_ipc1";

	interrupt-controller;

	#interrupt-cells = <3>;

};

spss {

	...

	glink {

		qcom,remote-pid = <8>;

		mboxes = <&sp_scsr 0>;

		mbox-names = "spss_spss";

		interrupts = <&intsp 0 0 IRQ_TYPE_EDGE_RISING>;

	};

};

Qualcomm Technologies, Inc. Secure Execution Environment IPC Interrupt Bridge

[Root level node]

Required properties:

-compatible : should be "qcom,qsee-ipc-irq-bridge";

[Second level nodes]

qcom,qsee-ipc-irq-subsystem

Required properties:

-qcom,dev-name: the bridge device name

-interrupt: IPC interrupt line from remote subsystem to QSEE

-label : The name of this subsystem.

Required properties if interrupt type is IRQ_TYPE_LEVEL_HIGH[4]:

-qcom,rx-irq-clr : the register to clear the level triggered rx interrupt

-qcom,rx-irq-clr-mask : the bitmask to clear the rx interrupt

Example:

	qcom,qsee_ipc_irq_bridge {

		compatible = "qcom,qsee-ipc-irq-bridge";

		qcom,qsee-ipc-irq-spss {

			qcom,rx-irq-clr = <0x1d08008 0x4>;

			qcom,rx-irq-clr-mask = <0x2>;

			qcom,dev-name = "qsee_ipc_irq_spss";

			interrupts = <0 349 4>;

			label = "spss";

		};

	};