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Commit f8ada189 authored by Xu YiPing's avatar Xu YiPing Committed by Will Deacon
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arm64: perf: remove unsupported events for Cortex-A73 



bus access read/write events are not supported in A73, based on the
Cortex-A73 TRM r0p2, section 11.9 Events (pages 11-457 to 11-460).

Fixes: 5561b6c5 "arm64: perf: add support for Cortex-A73"
Acked-by: default avatarJulien Thierry <julien.thierry@arm.com>
Signed-off-by: default avatarXu YiPing <xuyiping@hisilicon.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 9de52a75

arch/arm64/kernel/perf_event.c

+0 −6
Original line number Diff line number Diff line
@@ -262,12 +262,6 @@ static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 


	[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,

	[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)]	= ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,



	[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,

	[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,



	[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,

	[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,

};



static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]