Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 5561b6c5 authored by Julien Thierry's avatar Julien Thierry Committed by Will Deacon
Browse files

arm64: perf: add support for Cortex-A73 



The Cortex-A73 uses some implementation defined perf events.

This patch sets up the necessary mapping for Cortex-A73.

Mappings are based on Cortex-A73 TRM r0p2, section 11.9 Events
(pages 11-457 to 11-460).

Signed-off-by: default avatarJulien Thierry <julien.thierry@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent d0d09d4d

Documentation/devicetree/bindings/arm/pmu.txt

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ Required properties: 
- compatible : should be one of

	"apm,potenza-pmu"

	"arm,armv8-pmuv3"

	"arm,cortex-a73-pmu"

	"arm,cortex-a72-pmu"

	"arm,cortex-a57-pmu"

	"arm,cortex-a53-pmu"

arch/arm64/kernel/perf_event.c

+37 −0
Original line number Diff line number Diff line
@@ -255,6 +255,21 @@ static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
	[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,

};



static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]

					      [PERF_COUNT_HW_CACHE_OP_MAX]

					      [PERF_COUNT_HW_CACHE_RESULT_MAX] = {

	PERF_CACHE_MAP_ALL_UNSUPPORTED,



	[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,

	[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)]	= ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,



	[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,

	[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,



	[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,

	[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,

};



static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]

						   [PERF_COUNT_HW_CACHE_OP_MAX]

						   [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
@@ -868,6 +883,11 @@ static int armv8_a57_map_event(struct perf_event *event) 
	return __armv8_pmuv3_map_event(event, NULL, &armv8_a57_perf_cache_map);

}



static int armv8_a73_map_event(struct perf_event *event)

{

	return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map);

}



static int armv8_thunder_map_event(struct perf_event *event)

{

	return __armv8_pmuv3_map_event(event, NULL,
@@ -1018,6 +1038,22 @@ static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu) 
	return 0;

}



static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)

{

	int ret = armv8_pmu_init(cpu_pmu);

	if (ret)

		return ret;



	cpu_pmu->name			= "armv8_cortex_a73";

	cpu_pmu->map_event		= armv8_a73_map_event;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =

		&armv8_pmuv3_events_attr_group;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =

		&armv8_pmuv3_format_attr_group;



	return 0;

}



static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)

{

	int ret = armv8_pmu_init(cpu_pmu);
@@ -1055,6 +1091,7 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = { 
	{.compatible = "arm,cortex-a53-pmu",	.data = armv8_a53_pmu_init},

	{.compatible = "arm,cortex-a57-pmu",	.data = armv8_a57_pmu_init},

	{.compatible = "arm,cortex-a72-pmu",	.data = armv8_a72_pmu_init},

	{.compatible = "arm,cortex-a73-pmu",	.data = armv8_a73_pmu_init},

	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},

	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},

	{},