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Commit f213ad38 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc 

Pull sparc updates from David Miller:

 1) Recognize M8 cpus, just basic chip ID matching, from Allen Pais.

 2) Prevent crashes when bringing up sunvdc virtual block devices in
    some environments. From Jim Quigley.

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc:
  sunvdc: prevent sunvdc panic when mpgroup disk added to guest domain
  sparc64: Increase max_phys_bits to 51 and VA bits to 53 for M8.
  sparc64: recognize and support sparc M8 cpu type
  sparc64: properly name the cpu constants
parents 8d31f80e 3ee70591

arch/sparc/include/asm/spitfire.h

+16 −0
Original line number Diff line number Diff line
@@ -47,10 +47,26 @@ 
#define SUN4V_CHIP_NIAGARA5	0x05

#define SUN4V_CHIP_SPARC_M6	0x06

#define SUN4V_CHIP_SPARC_M7	0x07

#define SUN4V_CHIP_SPARC_M8	0x08

#define SUN4V_CHIP_SPARC64X	0x8a

#define SUN4V_CHIP_SPARC_SN	0x8b

#define SUN4V_CHIP_UNKNOWN	0xff



/*

 * The following CPU_ID_xxx constants are used

 * to identify the CPU type in the setup phase

 * (see head_64.S)

 */

#define CPU_ID_NIAGARA1		('1')

#define CPU_ID_NIAGARA2		('2')

#define CPU_ID_NIAGARA3		('3')

#define CPU_ID_NIAGARA4		('4')

#define CPU_ID_NIAGARA5		('5')

#define CPU_ID_M6		('6')

#define CPU_ID_M7		('7')

#define CPU_ID_M8		('8')

#define CPU_ID_SONOMA1		('N')



#ifndef __ASSEMBLY__



enum ultra_tlb_layout {

arch/sparc/kernel/cpu.c

+6 −0
Original line number Diff line number Diff line
@@ -506,6 +506,12 @@ static void __init sun4v_cpu_probe(void) 
		sparc_pmu_type = "sparc-m7";

		break;



	case SUN4V_CHIP_SPARC_M8:

		sparc_cpu_type = "SPARC-M8";

		sparc_fpu_type = "SPARC-M8 integrated FPU";

		sparc_pmu_type = "sparc-m8";

		break;



	case SUN4V_CHIP_SPARC_SN:

		sparc_cpu_type = "SPARC-SN";

		sparc_fpu_type = "SPARC-SN integrated FPU";

arch/sparc/kernel/cpumap.c

+1 −0
Original line number Diff line number Diff line
@@ -328,6 +328,7 @@ static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index) 
	case SUN4V_CHIP_NIAGARA5:

	case SUN4V_CHIP_SPARC_M6:

	case SUN4V_CHIP_SPARC_M7:

	case SUN4V_CHIP_SPARC_M8:

	case SUN4V_CHIP_SPARC_SN:

	case SUN4V_CHIP_SPARC64X:

		rover_inc_table = niagara_iterate_method;

arch/sparc/kernel/head_64.S

+14 −8
Original line number Diff line number Diff line
@@ -424,22 +424,25 @@ EXPORT_SYMBOL(sun4v_chip_type) 
	 nop



70:	ldub	[%g1 + 7], %g2

	cmp	%g2, '3'

	cmp	%g2, CPU_ID_NIAGARA3

	be,pt	%xcc, 5f

	 mov	SUN4V_CHIP_NIAGARA3, %g4

	cmp	%g2, '4'

	cmp	%g2, CPU_ID_NIAGARA4

	be,pt	%xcc, 5f

	 mov	SUN4V_CHIP_NIAGARA4, %g4

	cmp	%g2, '5'

	cmp	%g2, CPU_ID_NIAGARA5

	be,pt	%xcc, 5f

	 mov	SUN4V_CHIP_NIAGARA5, %g4

	cmp	%g2, '6'

	cmp	%g2, CPU_ID_M6

	be,pt	%xcc, 5f

	 mov	SUN4V_CHIP_SPARC_M6, %g4

	cmp	%g2, '7'

	cmp	%g2, CPU_ID_M7

	be,pt	%xcc, 5f

	 mov	SUN4V_CHIP_SPARC_M7, %g4

	cmp	%g2, 'N'

	cmp	%g2, CPU_ID_M8

	be,pt	%xcc, 5f

	 mov	SUN4V_CHIP_SPARC_M8, %g4

	cmp	%g2, CPU_ID_SONOMA1

	be,pt	%xcc, 5f

	 mov	SUN4V_CHIP_SPARC_SN, %g4

	ba,pt	%xcc, 49f
@@ -448,10 +451,10 @@ EXPORT_SYMBOL(sun4v_chip_type) 
91:	sethi	%hi(prom_cpu_compatible), %g1

	or	%g1, %lo(prom_cpu_compatible), %g1

	ldub	[%g1 + 17], %g2

	cmp	%g2, '1'

	cmp	%g2, CPU_ID_NIAGARA1

	be,pt	%xcc, 5f

	 mov	SUN4V_CHIP_NIAGARA1, %g4

	cmp	%g2, '2'

	cmp	%g2, CPU_ID_NIAGARA2

	be,pt	%xcc, 5f

	 mov	SUN4V_CHIP_NIAGARA2, %g4
@@ -600,6 +603,9 @@ niagara_tlb_fixup: 
	be,pt	%xcc, niagara4_patch

	 nop

	cmp	%g1, SUN4V_CHIP_SPARC_M7

	be,pt	%xcc, niagara4_patch

	 nop

	cmp	%g1, SUN4V_CHIP_SPARC_M8

	be,pt	%xcc, niagara4_patch

	 nop

	cmp	%g1, SUN4V_CHIP_SPARC_SN

arch/sparc/kernel/setup_64.c

+13 −2
Original line number Diff line number Diff line
@@ -288,10 +288,17 @@ static void __init sun4v_patch(void) 


	sun4v_patch_2insn_range(&__sun4v_2insn_patch,

				&__sun4v_2insn_patch_end);

	if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||

	    sun4v_chip_type == SUN4V_CHIP_SPARC_SN)



	switch (sun4v_chip_type) {

	case SUN4V_CHIP_SPARC_M7:

	case SUN4V_CHIP_SPARC_M8:

	case SUN4V_CHIP_SPARC_SN:

		sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,

					 &__sun_m7_2insn_patch_end);

		break;

	default:

		break;

	}



	sun4v_hvapi_init();

}
@@ -529,6 +536,7 @@ static void __init init_sparc64_elf_hwcap(void) 
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||

		    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||

		    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||

		    sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||

		    sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||

		    sun4v_chip_type == SUN4V_CHIP_SPARC64X)

			cap |= HWCAP_SPARC_BLKINIT;
@@ -538,6 +546,7 @@ static void __init init_sparc64_elf_hwcap(void) 
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||

		    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||

		    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||

		    sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||

		    sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||

		    sun4v_chip_type == SUN4V_CHIP_SPARC64X)

			cap |= HWCAP_SPARC_N2;
@@ -568,6 +577,7 @@ static void __init init_sparc64_elf_hwcap(void) 
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||

			    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||

			    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||

			    sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||

			    sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||

			    sun4v_chip_type == SUN4V_CHIP_SPARC64X)

				cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
@@ -578,6 +588,7 @@ static void __init init_sparc64_elf_hwcap(void) 
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||

			    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||

			    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||

			    sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||

			    sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||

			    sun4v_chip_type == SUN4V_CHIP_SPARC64X)

				cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |