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Commit 8d31f80e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v4.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control fixes from Linus Walleij:
 "These are the pin control fixes I have gathered since the return from
  my vacation. They boiled in -next a while so let's get them in.

  Apart from the documentation build it is purely driver fixes. Which is
  nice. The Intel fixes seem kind of important.

   - Fix the documentation build as the docs were moved

   - Correct the UART pin list on the Intel Merrifield

   - Fix pin assignment and number of pins on the Marvell Armada 37xx
     pin controller

   - Cover the Setzer models in the Chromebook DMI quirk in the Intel
     cheryview driver so they start working

   - Add the missing "sim" function to the sunxi driver

   - Fix USB pin definitions on Uniphier Pro4

   - Smatch fix for invalid reference in the zx pin control driver"

* tag 'pinctrl-v4.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: generic: update references to Documentation/pinctrl.txt
  pinctrl: intel: merrifield: Correct UART pin lists
  pinctrl: armada-37xx: Fix number of pin in south bridge
  pinctrl: armada-37xx: Fix the pin 23 on south bridge
  pinctrl: cherryview: Add Setzer models to the Chromebook DMI quirk
  pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver
  pinctrl: uniphier: fix USB3 pin assignment for Pro4
  pinctrl: zte: fix dereference of 'data' in zx_set_mux()
parents 48fb6f4d 0cca6c89

Documentation/gpio/gpio-legacy.txt

+1 −1
Original line number Diff line number Diff line
@@ -459,7 +459,7 @@ pin controller? 


This is done by registering "ranges" of pins, which are essentially

cross-reference tables. These are described in

Documentation/pinctrl.txt

Documentation/driver-api/pinctl.rst



While the pin allocation is totally managed by the pinctrl subsystem,

gpio (under gpiolib) is still maintained by gpio drivers. It may happen

MAINTAINERS

+1 −1
Original line number Diff line number Diff line
@@ -10383,7 +10383,7 @@ L: linux-gpio@vger.kernel.org 
T:	git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git

S:	Maintained

F:	Documentation/devicetree/bindings/pinctrl/

F:	Documentation/pinctrl.txt

F:	Documentation/driver-api/pinctl.rst

F:	drivers/pinctrl/

F:	include/linux/pinctrl/

drivers/pinctrl/intel/pinctrl-cherryview.c

+7 −0
Original line number Diff line number Diff line
@@ -1547,6 +1547,13 @@ static const struct dmi_system_id chv_no_valid_mask[] = { 
			DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),

		},

	},

	{

		.ident = "HP Chromebook 11 G5 (Setzer)",

		.matches = {

			DMI_MATCH(DMI_SYS_VENDOR, "HP"),

			DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),

		},

	},

	{

		.ident = "Acer Chromebook R11 (Cyan)",

		.matches = {

drivers/pinctrl/intel/pinctrl-merrifield.c

+3 −3
Original line number Diff line number Diff line
@@ -343,9 +343,9 @@ static const struct pinctrl_pin_desc mrfld_pins[] = { 


static const unsigned int mrfld_sdio_pins[] = { 50, 51, 52, 53, 54, 55, 56 };

static const unsigned int mrfld_spi5_pins[] = { 90, 91, 92, 93, 94, 95, 96 };

static const unsigned int mrfld_uart0_pins[] = { 124, 125, 126, 127 };

static const unsigned int mrfld_uart1_pins[] = { 128, 129, 130, 131 };

static const unsigned int mrfld_uart2_pins[] = { 132, 133, 134, 135 };

static const unsigned int mrfld_uart0_pins[] = { 115, 116, 117, 118 };

static const unsigned int mrfld_uart1_pins[] = { 119, 120, 121, 122 };

static const unsigned int mrfld_uart2_pins[] = { 123, 124, 125, 126 };

static const unsigned int mrfld_pwm0_pins[] = { 144 };

static const unsigned int mrfld_pwm1_pins[] = { 145 };

static const unsigned int mrfld_pwm2_pins[] = { 132 };

drivers/pinctrl/mvebu/pinctrl-armada-37xx.c

+18 −7
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ 
#define IRQ_STATUS	0x10

#define IRQ_WKUP	0x18



#define NB_FUNCS 2

#define NB_FUNCS 3

#define GPIO_PER_REG	32



/**
@@ -126,6 +126,16 @@ struct armada_37xx_pinctrl { 
		.funcs = {_func1, "gpio"}	\

	}



#define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \

	{					\

		.name = _name,			\

		.start_pin = _start,		\

		.npins = _nr,			\

		.reg_mask = _mask,		\

		.val = {_v1, _v2, _v3},	\

		.funcs = {_f1, _f2, "gpio"}	\

	}



#define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \

		      _f1, _f2)				\

	{						\
@@ -171,12 +181,13 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { 
	PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),

	PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),

	PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),

	PIN_GRP_EXTRA("rgmii", 6, 12, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"),

	PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),

	PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),

	PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),

	PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),

	PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),

	PIN_GRP("mii_col", 23, 1, BIT(8), "mii", "mii_err"),

	PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),

		       "mii", "mii_err"),

};



const struct armada_37xx_pin_data armada_37xx_pin_nb = {
@@ -187,7 +198,7 @@ const struct armada_37xx_pin_data armada_37xx_pin_nb = { 
};



const struct armada_37xx_pin_data armada_37xx_pin_sb = {

	.nr_pins = 29,

	.nr_pins = 30,

	.name = "GPIO2",

	.groups = armada_37xx_sb_groups,

	.ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
@@ -208,7 +219,7 @@ static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp, 
{

	int f;



	for (f = 0; f < NB_FUNCS; f++)

	for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)

		if (!strcmp(grp->funcs[f], func))

			return f;
@@ -795,7 +806,7 @@ static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info) 
		for (j = 0; j < grp->extra_npins; j++)

			grp->pins[i+j] = grp->extra_pin + j;



		for (f = 0; f < NB_FUNCS; f++) {

		for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {

			int ret;

			/* check for unique functions and count groups */

			ret = armada_37xx_add_function(info->funcs, &funcsize,
@@ -847,7 +858,7 @@ static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info) 
			struct armada_37xx_pin_group *gp = &info->groups[g];

			int f;



			for (f = 0; f < NB_FUNCS; f++) {

			for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {

				if (strcmp(gp->funcs[f], name) == 0) {

					*groups = gp->name;

					groups++;