Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f127fa09 authored by Alexander Shishkin's avatar Alexander Shishkin Committed by Ingo Molnar
Browse files

perf/x86/intel/pt: Add IP filtering register/CPUID bits 



New versions of Intel PT support address range-based filtering. Add
the new registers, bit definitions and relevant CPUID bits.

Signed-off-by: default avatarAlexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: vince@deater.net
Link: http://lkml.kernel.org/r/1461771888-10409-4-git-send-email-alexander.shishkin@linux.intel.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 0dd28e2c

arch/x86/events/intel/pt.c

+2 −0
Original line number Diff line number Diff line
@@ -67,11 +67,13 @@ static struct pt_cap_desc { 
	PT_CAP(max_subleaf,		0, CR_EAX, 0xffffffff),

	PT_CAP(cr3_filtering,		0, CR_EBX, BIT(0)),

	PT_CAP(psb_cyc,			0, CR_EBX, BIT(1)),

	PT_CAP(ip_filtering,		0, CR_EBX, BIT(2)),

	PT_CAP(mtc,			0, CR_EBX, BIT(3)),

	PT_CAP(topa_output,		0, CR_ECX, BIT(0)),

	PT_CAP(topa_multiple_entries,	0, CR_ECX, BIT(1)),

	PT_CAP(single_range_output,	0, CR_ECX, BIT(2)),

	PT_CAP(payloads_lip,		0, CR_ECX, BIT(31)),

	PT_CAP(num_address_ranges,	1, CR_EAX, 0x3),

	PT_CAP(mtc_periods,		1, CR_EAX, 0xffff0000),

	PT_CAP(cycle_thresholds,	1, CR_EBX, 0xffff),

	PT_CAP(psb_periods,		1, CR_EBX, 0xffff0000),

arch/x86/events/intel/pt.h

+12 −0
Original line number Diff line number Diff line
@@ -38,8 +38,18 @@ 
#define RTIT_CTL_CYC_THRESH		(0x0full << RTIT_CTL_CYC_THRESH_OFFSET)

#define RTIT_CTL_PSB_FREQ_OFFSET	24

#define RTIT_CTL_PSB_FREQ      		(0x0full << RTIT_CTL_PSB_FREQ_OFFSET)

#define RTIT_CTL_ADDR0_OFFSET		32

#define RTIT_CTL_ADDR0      		(0x0full << RTIT_CTL_ADDR0_OFFSET)

#define RTIT_CTL_ADDR1_OFFSET		36

#define RTIT_CTL_ADDR1      		(0x0full << RTIT_CTL_ADDR1_OFFSET)

#define RTIT_CTL_ADDR2_OFFSET		40

#define RTIT_CTL_ADDR2      		(0x0full << RTIT_CTL_ADDR2_OFFSET)

#define RTIT_CTL_ADDR3_OFFSET		44

#define RTIT_CTL_ADDR3      		(0x0full << RTIT_CTL_ADDR3_OFFSET)

#define RTIT_STATUS_FILTEREN		BIT(0)

#define RTIT_STATUS_CONTEXTEN		BIT(1)

#define RTIT_STATUS_TRIGGEREN		BIT(2)

#define RTIT_STATUS_BUFFOVF		BIT(3)

#define RTIT_STATUS_ERROR		BIT(4)

#define RTIT_STATUS_STOPPED		BIT(5)
@@ -76,11 +86,13 @@ enum pt_capabilities { 
	PT_CAP_max_subleaf = 0,

	PT_CAP_cr3_filtering,

	PT_CAP_psb_cyc,

	PT_CAP_ip_filtering,

	PT_CAP_mtc,

	PT_CAP_topa_output,

	PT_CAP_topa_multiple_entries,

	PT_CAP_single_range_output,

	PT_CAP_payloads_lip,

	PT_CAP_num_address_ranges,

	PT_CAP_mtc_periods,

	PT_CAP_cycle_thresholds,

	PT_CAP_psb_periods,

arch/x86/include/asm/msr-index.h

+9 −0
Original line number Diff line number Diff line
@@ -90,6 +90,15 @@ 


#define MSR_IA32_RTIT_CTL		0x00000570

#define MSR_IA32_RTIT_STATUS		0x00000571

#define MSR_IA32_RTIT_STATUS		0x00000571

#define MSR_IA32_RTIT_ADDR0_A		0x00000580

#define MSR_IA32_RTIT_ADDR0_B		0x00000581

#define MSR_IA32_RTIT_ADDR1_A		0x00000582

#define MSR_IA32_RTIT_ADDR1_B		0x00000583

#define MSR_IA32_RTIT_ADDR2_A		0x00000584

#define MSR_IA32_RTIT_ADDR2_B		0x00000585

#define MSR_IA32_RTIT_ADDR3_A		0x00000586

#define MSR_IA32_RTIT_ADDR3_B		0x00000587

#define MSR_IA32_RTIT_CR3_MATCH		0x00000572

#define MSR_IA32_RTIT_OUTPUT_BASE	0x00000560

#define MSR_IA32_RTIT_OUTPUT_MASK	0x00000561