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Commit 0dd28e2c authored by Alexander Shishkin's avatar Alexander Shishkin Committed by Ingo Molnar
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perf/x86/intel/pt: Move PT specific MSR bit definitions to a private header 



Nothing outside of the Intel PT driver should ever care about its MSR
bits, so there is no reason to keep them in msr-index.h. This patch
moves them to a pt-local header.

Signed-off-by: default avatarAlexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: vince@deater.net
Link: http://lkml.kernel.org/r/1461771888-10409-3-git-send-email-alexander.shishkin@linux.intel.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent c796bbbe

arch/x86/events/intel/pt.h

+24 −0
Original line number Diff line number Diff line
@@ -19,6 +19,30 @@ 
#ifndef __INTEL_PT_H__

#define __INTEL_PT_H__



/*

 * PT MSR bit definitions

 */

#define RTIT_CTL_TRACEEN		BIT(0)

#define RTIT_CTL_CYCLEACC		BIT(1)

#define RTIT_CTL_OS			BIT(2)

#define RTIT_CTL_USR			BIT(3)

#define RTIT_CTL_CR3EN			BIT(7)

#define RTIT_CTL_TOPA			BIT(8)

#define RTIT_CTL_MTC_EN			BIT(9)

#define RTIT_CTL_TSC_EN			BIT(10)

#define RTIT_CTL_DISRETC		BIT(11)

#define RTIT_CTL_BRANCH_EN		BIT(13)

#define RTIT_CTL_MTC_RANGE_OFFSET	14

#define RTIT_CTL_MTC_RANGE		(0x0full << RTIT_CTL_MTC_RANGE_OFFSET)

#define RTIT_CTL_CYC_THRESH_OFFSET	19

#define RTIT_CTL_CYC_THRESH		(0x0full << RTIT_CTL_CYC_THRESH_OFFSET)

#define RTIT_CTL_PSB_FREQ_OFFSET	24

#define RTIT_CTL_PSB_FREQ      		(0x0full << RTIT_CTL_PSB_FREQ_OFFSET)

#define RTIT_STATUS_CONTEXTEN		BIT(1)

#define RTIT_STATUS_TRIGGEREN		BIT(2)

#define RTIT_STATUS_ERROR		BIT(4)

#define RTIT_STATUS_STOPPED		BIT(5)



/*

 * Single-entry ToPA: when this close to region boundary, switch

 * buffers to avoid losing data.

arch/x86/include/asm/msr-index.h

+0 −20
Original line number Diff line number Diff line
@@ -89,27 +89,7 @@ 
#define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6



#define MSR_IA32_RTIT_CTL		0x00000570

#define RTIT_CTL_TRACEEN		BIT(0)

#define RTIT_CTL_CYCLEACC		BIT(1)

#define RTIT_CTL_OS			BIT(2)

#define RTIT_CTL_USR			BIT(3)

#define RTIT_CTL_CR3EN			BIT(7)

#define RTIT_CTL_TOPA			BIT(8)

#define RTIT_CTL_MTC_EN			BIT(9)

#define RTIT_CTL_TSC_EN			BIT(10)

#define RTIT_CTL_DISRETC		BIT(11)

#define RTIT_CTL_BRANCH_EN		BIT(13)

#define RTIT_CTL_MTC_RANGE_OFFSET	14

#define RTIT_CTL_MTC_RANGE		(0x0full << RTIT_CTL_MTC_RANGE_OFFSET)

#define RTIT_CTL_CYC_THRESH_OFFSET	19

#define RTIT_CTL_CYC_THRESH		(0x0full << RTIT_CTL_CYC_THRESH_OFFSET)

#define RTIT_CTL_PSB_FREQ_OFFSET	24

#define RTIT_CTL_PSB_FREQ      		(0x0full << RTIT_CTL_PSB_FREQ_OFFSET)

#define MSR_IA32_RTIT_STATUS		0x00000571

#define RTIT_STATUS_CONTEXTEN		BIT(1)

#define RTIT_STATUS_TRIGGEREN		BIT(2)

#define RTIT_STATUS_ERROR		BIT(4)

#define RTIT_STATUS_STOPPED		BIT(5)

#define MSR_IA32_RTIT_CR3_MATCH		0x00000572

#define MSR_IA32_RTIT_OUTPUT_BASE	0x00000560

#define MSR_IA32_RTIT_OUTPUT_MASK	0x00000561