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Commit f1017969 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard
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clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6



The pll6 has a /4 output that is used as an input to the ahb mux clock.

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 934fe5f4
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