Loading drivers/bus/mhi/core/mhi_internal.h +1 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,7 @@ extern struct bus_type mhi_bus_type; /* MHI mmio register mapping */ #define PCI_INVALID_READ(val) (val == U32_MAX) #define MHI_REG_SIZE (SZ_4K) #define MHIREGLEN (0x0) #define MHIREGLEN_MHIREGLEN_MASK (0xFFFFFFFF) Loading drivers/bus/mhi/core/mhi_main.c +4 −2 Original line number Diff line number Diff line Loading @@ -81,7 +81,9 @@ int mhi_get_capability_offset(struct mhi_controller *mhi_cntrl, if (ret) return ret; *offset += next_offset; *offset = next_offset; if (*offset >= MHI_REG_SIZE) return -ENXIO; } while (next_offset); return -ENXIO; Loading Loading @@ -1241,7 +1243,7 @@ int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl, break; } default: MHI_ASSERT(1, "Unsupported ev type"); MHI_ERR("Unhandled Event: 0x%x\n", type); break; } Loading Loading
drivers/bus/mhi/core/mhi_internal.h +1 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,7 @@ extern struct bus_type mhi_bus_type; /* MHI mmio register mapping */ #define PCI_INVALID_READ(val) (val == U32_MAX) #define MHI_REG_SIZE (SZ_4K) #define MHIREGLEN (0x0) #define MHIREGLEN_MHIREGLEN_MASK (0xFFFFFFFF) Loading
drivers/bus/mhi/core/mhi_main.c +4 −2 Original line number Diff line number Diff line Loading @@ -81,7 +81,9 @@ int mhi_get_capability_offset(struct mhi_controller *mhi_cntrl, if (ret) return ret; *offset += next_offset; *offset = next_offset; if (*offset >= MHI_REG_SIZE) return -ENXIO; } while (next_offset); return -ENXIO; Loading Loading @@ -1241,7 +1243,7 @@ int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl, break; } default: MHI_ASSERT(1, "Unsupported ev type"); MHI_ERR("Unhandled Event: 0x%x\n", type); break; } Loading