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Commit e650ce0f authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: Octeon: Don't request interrupts for unused IPI mailbox bits. 



We only use the three low-order mailbox bits.  Leave the upper bits alone
for possible use by drivers and other software.

Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2090/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 7716e654

arch/mips/cavium-octeon/smp.c

+7 −8
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ static irqreturn_t mailbox_interrupt(int irq, void *dev_id) 
	uint64_t action;



	/* Load the mailbox register to figure out what we're supposed to do */

	action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid));

	action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff;



	/* Clear the mailbox to clear the interrupt */

	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
@@ -200,16 +200,15 @@ void octeon_prepare_cpus(unsigned int max_cpus) 
	if (labi->labi_signature != LABI_SIGNATURE)

		panic("The bootloader version on this board is incorrect.");

#endif



	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff);

	/*

	 * Only the low order mailbox bits are used for IPIs, leave

	 * the other bits alone.

	 */

	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);

	if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED,

			"mailbox0", mailbox_interrupt)) {

			"SMP-IPI", mailbox_interrupt)) {

		panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");

	}

	if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_DISABLED,

			"mailbox1", mailbox_interrupt)) {

		panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n");

	}

}



/**