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Commit 7716e654 authored by Chandrakala Chavva's avatar Chandrakala Chavva Committed by Ralf Baechle
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Octeon: Fix interrupt irq settings for performance counters. 



Octeon uses different interrupt irq for timer and performance counters.
Set CvmCtl[IPPCI] to correct irq value very early.

Signed-off-by: default avatarChandrakala Chavva <cchavva@caviumnetworks.com>
Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/2085/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent b32ee693

arch/mips/cavium-octeon/setup.c

+0 −7
Original line number Diff line number Diff line
@@ -288,7 +288,6 @@ void octeon_user_io_init(void) 
	union octeon_cvmemctl cvmmemctl;

	union cvmx_iob_fau_timeout fau_timeout;

	union cvmx_pow_nw_tim nm_tim;

	uint64_t cvmctl;



	/* Get the current settings for CP0_CVMMEMCTL_REG */

	cvmmemctl.u64 = read_c0_cvmmemctl();
@@ -392,12 +391,6 @@ void octeon_user_io_init(void) 
			  CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,

			  CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);



	/* Move the performance counter interrupts to IRQ 6 */

	cvmctl = read_c0_cvmctl();

	cvmctl &= ~(7 << 7);

	cvmctl |= 6 << 7;

	write_c0_cvmctl(cvmctl);



	/* Set a default for the hardware timeouts */

	fau_timeout.u64 = 0;

	fau_timeout.s.tout_val = 0xfff;

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

+5 −0
Original line number Diff line number Diff line
@@ -63,6 +63,11 @@ 
	# CN30XX Disable instruction prefetching

	or  v0, v0, 0x2000

skip:

	# First clear off CvmCtl[IPPCI] bit and move the performance

	# counters interrupt to IRQ 6

	li	v1, ~(7 << 7)

	and	v0, v0, v1

	ori	v0, v0, (6 << 7)

	# Write the cavium control register

	dmtc0   v0, CP0_CVMCTL_REG

	sync