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Commit e5d04670 authored by Ramon Fried's avatar Ramon Fried Committed by Kalle Valo
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wcn36xx: calculate DXE default channel values 



DXE channel defaults used hardcoded magic values.
Added bit definitions of the control register and
calculate this values in compilation for clarity.

Signed-off-by: default avatarRamon Fried <rfried@codeaurora.org>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent 6ced7958

drivers/net/wireless/ath/wcn36xx/dxe.h

+99 −5
Original line number Diff line number Diff line
@@ -140,12 +140,106 @@ H2H_TEST_RX_TX = DMA2 
#define WCN36XX_DXE_WQ_RX_L			0xB

#define WCN36XX_DXE_WQ_RX_H			0x4



/* TODO This must calculated properly but not hardcoded */

/* Channel enable or restart */

#define WCN36xx_DXE_CH_CTRL_EN			BIT(0)

/* End of packet bit */

#define WCN36xx_DXE_CH_CTRL_EOP			BIT(3)

/* BD Handling bit */

#define WCN36xx_DXE_CH_CTRL_BDH			BIT(4)

/* Source is queue */

#define WCN36xx_DXE_CH_CTRL_SIQ			BIT(5)

/* Destination is queue */

#define WCN36xx_DXE_CH_CTRL_DIQ			BIT(6)

/* Pointer descriptor is queue */

#define WCN36xx_DXE_CH_CTRL_PIQ			BIT(7)

/* Relase PDU when done */

#define WCN36xx_DXE_CH_CTRL_PDU_REL		BIT(8)

/* Stop channel processing */

#define WCN36xx_DXE_CH_CTRL_STOP		BIT(16)

/* Enable external descriptor interrupt */

#define WCN36xx_DXE_CH_CTRL_INE_ED		BIT(17)

/* Enable channel interrupt on errors */

#define WCN36xx_DXE_CH_CTRL_INE_ERR		BIT(18)

/* Enable Channel interrupt when done */

#define WCN36xx_DXE_CH_CTRL_INE_DONE	BIT(19)

/* External descriptor enable */

#define WCN36xx_DXE_CH_CTRL_EDEN		BIT(20)

/* Wait for valid bit */

#define WCN36xx_DXE_CH_CTRL_EDVEN		BIT(21)

/* Endianness is little endian*/

#define WCN36xx_DXE_CH_CTRL_ENDIANNESS	BIT(26)

/* Abort transfer */

#define WCN36xx_DXE_CH_CTRL_ABORT		BIT(27)

/* Long descriptor format */

#define WCN36xx_DXE_CH_CTRL_DFMT		BIT(28)

/* Endian byte swap enable */

#define WCN36xx_DXE_CH_CTRL_SWAP		BIT(31)



/* Transfer type */

#define WCN36xx_DXE_CH_CTRL_XTYPE_SHIFT 1

#define WCN36xx_DXE_CH_CTRL_XTYPE_MASK GENMASK(2, WCN36xx_DXE_CH_CTRL_XTYPE_SHIFT)

#define WCN36xx_DXE_CH_CTRL_XTYPE_SET(x)	((x) << WCN36xx_DXE_CH_CTRL_XTYPE_SHIFT)



/* Channel BMU Threshold select */

#define WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SHIFT 9

#define WCN36xx_DXE_CH_CTRL_BTHLD_SEL_MASK GENMASK(12, WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SHIFT)

#define WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(x) ((x) << WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SHIFT)



/* Channel Priority */

#define WCN36xx_DXE_CH_CTRL_PRIO_SHIFT 13

#define WCN36xx_DXE_CH_CTRL_PRIO_MASK GENMASK(15, WCN36xx_DXE_CH_CTRL_PRIO_SHIFT)

#define WCN36xx_DXE_CH_CTRL_PRIO_SET(x) ((x) << WCN36xx_DXE_CH_CTRL_PRIO_SHIFT)



/* Counter select */

#define WCN36xx_DXE_CH_CTRL_SEL_SHIFT 22

#define WCN36xx_DXE_CH_CTRL_SEL_MASK GENMASK(25, WCN36xx_DXE_CH_CTRL_SEL_SHIFT)

#define WCN36xx_DXE_CH_CTRL_SEL_SET(x)	((x) << WCN36xx_DXE_CH_CTRL_SEL_SHIFT)



/* Channel BD template index */

#define WCN36xx_DXE_CH_CTRL_BDT_IDX_SHIFT 29

#define WCN36xx_DXE_CH_CTRL_BDT_IDX_MASK GENMASK(30, WCN36xx_DXE_CH_CTRL_BDT_IDX_SHIFT)

#define WCN36xx_DXE_CH_CTRL_BDT_IDX_SET(x)	((x) << WCN36xx_DXE_CH_CTRL_BDT_IDX_SHIFT)



/* DXE default control register values */

#define WCN36XX_DXE_CH_DEFAULT_CTL_RX_L		0x847EAD2F

#define WCN36XX_DXE_CH_DEFAULT_CTL_RX_H		0x84FED12F

#define WCN36XX_DXE_CH_DEFAULT_CTL_TX_H		0x853ECF4D

#define WCN36XX_DXE_CH_DEFAULT_CTL_TX_L		0x843e8b4d

#define WCN36XX_DXE_CH_DEFAULT_CTL_RX_L (WCN36xx_DXE_CH_CTRL_EN | \

		WCN36xx_DXE_CH_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_B2H) | \

		WCN36xx_DXE_CH_CTRL_EOP | WCN36xx_DXE_CH_CTRL_SIQ | \

		WCN36xx_DXE_CH_CTRL_PDU_REL | WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(6) | \

		WCN36xx_DXE_CH_CTRL_PRIO_SET(5) | WCN36xx_DXE_CH_CTRL_INE_ED | \

		WCN36xx_DXE_CH_CTRL_INE_ERR | WCN36xx_DXE_CH_CTRL_INE_DONE | \

		WCN36xx_DXE_CH_CTRL_EDEN | WCN36xx_DXE_CH_CTRL_EDVEN | \

		WCN36xx_DXE_CH_CTRL_SEL_SET(1) | WCN36xx_DXE_CH_CTRL_ENDIANNESS | \

		WCN36xx_DXE_CH_CTRL_SWAP)



#define WCN36XX_DXE_CH_DEFAULT_CTL_RX_H (WCN36xx_DXE_CH_CTRL_EN | \

		WCN36xx_DXE_CH_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_B2H) | \

		WCN36xx_DXE_CH_CTRL_EOP | WCN36xx_DXE_CH_CTRL_SIQ | \

		WCN36xx_DXE_CH_CTRL_PDU_REL | WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(8) | \

		WCN36xx_DXE_CH_CTRL_PRIO_SET(6) | WCN36xx_DXE_CH_CTRL_INE_ED | \

		WCN36xx_DXE_CH_CTRL_INE_ERR | WCN36xx_DXE_CH_CTRL_INE_DONE | \

		WCN36xx_DXE_CH_CTRL_EDEN | WCN36xx_DXE_CH_CTRL_EDVEN | \

		WCN36xx_DXE_CH_CTRL_SEL_SET(3) | WCN36xx_DXE_CH_CTRL_ENDIANNESS | \

		WCN36xx_DXE_CH_CTRL_SWAP)



#define WCN36XX_DXE_CH_DEFAULT_CTL_TX_H	(WCN36xx_DXE_CH_CTRL_EN | \

		WCN36xx_DXE_CH_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \

		WCN36xx_DXE_CH_CTRL_EOP | WCN36xx_DXE_CH_CTRL_DIQ | \

		WCN36xx_DXE_CH_CTRL_PDU_REL | WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(7) | \

		WCN36xx_DXE_CH_CTRL_PRIO_SET(6) | WCN36xx_DXE_CH_CTRL_INE_ED | \

		WCN36xx_DXE_CH_CTRL_INE_ERR | WCN36xx_DXE_CH_CTRL_INE_DONE | \

		WCN36xx_DXE_CH_CTRL_EDEN | WCN36xx_DXE_CH_CTRL_EDVEN | \

		WCN36xx_DXE_CH_CTRL_SEL_SET(4) | WCN36xx_DXE_CH_CTRL_ENDIANNESS | \

		WCN36xx_DXE_CH_CTRL_SWAP)



#define WCN36XX_DXE_CH_DEFAULT_CTL_TX_L (WCN36xx_DXE_CH_CTRL_EN | \

		WCN36xx_DXE_CH_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \

		WCN36xx_DXE_CH_CTRL_EOP | WCN36xx_DXE_CH_CTRL_DIQ | \

		WCN36xx_DXE_CH_CTRL_PDU_REL | WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(5) | \

		WCN36xx_DXE_CH_CTRL_PRIO_SET(4) | WCN36xx_DXE_CH_CTRL_INE_ED | \

		WCN36xx_DXE_CH_CTRL_INE_ERR | WCN36xx_DXE_CH_CTRL_INE_DONE | \

		WCN36xx_DXE_CH_CTRL_EDEN | WCN36xx_DXE_CH_CTRL_EDVEN | \

		WCN36xx_DXE_CH_CTRL_SEL_SET(0) | WCN36xx_DXE_CH_CTRL_ENDIANNESS | \

		WCN36xx_DXE_CH_CTRL_SWAP)



/* Common DXE registers */

#define WCN36XX_DXE_MEM_CSR			(WCN36XX_DXE_MEM_REG + 0x00)