Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e59dc172 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Move cpu_cache_is_coherent() to header 



For use in the next patch, take the current is-coherent helper and add
it to i915_gem_object.h

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170222114049.28456-2-chris@chris-wilson.co.uk
parent 208b84a3

drivers/gpu/drm/i915/i915_drv.h

+6 −0
Original line number Diff line number Diff line
@@ -4097,4 +4097,10 @@ int remap_io_mapping(struct vm_area_struct *vma, 
		     unsigned long addr, unsigned long pfn, unsigned long size,

		     struct io_mapping *iomap);



static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)

{

	return (obj->cache_level != I915_CACHE_NONE ||

		HAS_LLC(to_i915(obj->base.dev)));

}



#endif

drivers/gpu/drm/i915/i915_gem.c

+6 −14
Original line number Diff line number Diff line
@@ -48,18 +48,12 @@ static void i915_gem_flush_free_objects(struct drm_i915_private *i915); 
static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);

static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);



static bool cpu_cache_is_coherent(struct drm_device *dev,

				  enum i915_cache_level level)

{

	return HAS_LLC(to_i915(dev)) || level != I915_CACHE_NONE;

}



static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)

{

	if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)

		return false;



	if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))

	if (!i915_gem_object_is_coherent(obj))

		return true;



	return obj->pin_display;
@@ -255,7 +249,7 @@ __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, 


	if (needs_clflush &&

	    (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 &&

	    !cpu_cache_is_coherent(obj->base.dev, obj->cache_level))

	    !i915_gem_object_is_coherent(obj))

		drm_clflush_sg(pages);



	obj->base.read_domains = I915_GEM_DOMAIN_CPU;
@@ -796,8 +790,7 @@ int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, 
	 * anyway again before the next pread happens.

	 */

	if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))

		*needs_clflush = !cpu_cache_is_coherent(obj->base.dev,

							obj->cache_level);

		*needs_clflush = !i915_gem_object_is_coherent(obj);



	if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {

		ret = i915_gem_object_set_to_cpu_domain(obj, false);
@@ -853,8 +846,7 @@ int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, 
	 * before writing.

	 */

	if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))

		*needs_clflush |= !cpu_cache_is_coherent(obj->base.dev,

							 obj->cache_level);

		*needs_clflush |= !i915_gem_object_is_coherent(obj);



	if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {

		ret = i915_gem_object_set_to_cpu_domain(obj, true);
@@ -3173,7 +3165,7 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj, 
	 * snooping behaviour occurs naturally as the result of our domain

	 * tracking.

	 */

	if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {

	if (!force && i915_gem_object_is_coherent(obj)) {

		obj->cache_dirty = true;

		return;

	}
@@ -3412,7 +3404,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 
	}



	if (obj->base.write_domain == I915_GEM_DOMAIN_CPU &&

	    cpu_cache_is_coherent(obj->base.dev, obj->cache_level))

	    i915_gem_object_is_coherent(obj))

		obj->cache_dirty = true;



	list_for_each_entry(vma, &obj->vma_list, obj_link)