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Commit 208b84a3 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Remove change_domain tracepoint 



The change_domain tracepoint has been inaccurate for a few years - it
doesn't fully capture the domains, especially with userspace bypassing
them. It is defunct, misleading and time to be removed.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170222114049.28456-1-chris@chris-wilson.co.uk
parent 1d6aa7a3

drivers/gpu/drm/i915/i915_gem.c

+0 −30
Original line number Diff line number Diff line
@@ -3214,9 +3214,6 @@ i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) 
	intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT));



	obj->base.write_domain = 0;

	trace_i915_gem_object_change_domain(obj,

					    obj->base.read_domains,

					    I915_GEM_DOMAIN_GTT);

}



/** Flushes the CPU write domain for the object if it's dirty. */
@@ -3230,9 +3227,6 @@ i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) 
	intel_fb_obj_flush(obj, false, ORIGIN_CPU);



	obj->base.write_domain = 0;

	trace_i915_gem_object_change_domain(obj,

					    obj->base.read_domains,

					    I915_GEM_DOMAIN_CPU);

}



/**
@@ -3246,7 +3240,6 @@ i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) 
int

i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)

{

	uint32_t old_write_domain, old_read_domains;

	int ret;



	lockdep_assert_held(&obj->base.dev->struct_mutex);
@@ -3284,9 +3277,6 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) 
	if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)

		mb();



	old_write_domain = obj->base.write_domain;

	old_read_domains = obj->base.read_domains;



	/* It should now be out of any other write domains, and we can update

	 * the domain values for our changes.

	 */
@@ -3298,10 +3288,6 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) 
		obj->mm.dirty = true;

	}



	trace_i915_gem_object_change_domain(obj,

					    old_read_domains,

					    old_write_domain);



	i915_gem_object_unpin_pages(obj);

	return 0;

}
@@ -3538,7 +3524,6 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 
				     const struct i915_ggtt_view *view)

{

	struct i915_vma *vma;

	u32 old_read_domains, old_write_domain;

	int ret;



	lockdep_assert_held(&obj->base.dev->struct_mutex);
@@ -3603,19 +3588,12 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 
		intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);

	}



	old_write_domain = obj->base.write_domain;

	old_read_domains = obj->base.read_domains;



	/* It should now be out of any other write domains, and we can update

	 * the domain values for our changes.

	 */

	obj->base.write_domain = 0;

	obj->base.read_domains |= I915_GEM_DOMAIN_GTT;



	trace_i915_gem_object_change_domain(obj,

					    old_read_domains,

					    old_write_domain);



	return vma;



err_unpin_display:
@@ -3651,7 +3629,6 @@ i915_gem_object_unpin_from_display_plane(struct i915_vma *vma) 
int

i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)

{

	uint32_t old_write_domain, old_read_domains;

	int ret;



	lockdep_assert_held(&obj->base.dev->struct_mutex);
@@ -3670,9 +3647,6 @@ i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) 


	i915_gem_object_flush_gtt_write_domain(obj);



	old_write_domain = obj->base.write_domain;

	old_read_domains = obj->base.read_domains;



	/* Flush the CPU cache if it's still invalid. */

	if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {

		i915_gem_clflush_object(obj, false);
@@ -3693,10 +3667,6 @@ i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) 
		obj->base.write_domain = I915_GEM_DOMAIN_CPU;

	}



	trace_i915_gem_object_change_domain(obj,

					    old_read_domains,

					    old_write_domain);



	return 0;

}

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+0 −3
Original line number Diff line number Diff line
@@ -1317,8 +1317,6 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas, 


	list_for_each_entry(vma, vmas, exec_list) {

		struct drm_i915_gem_object *obj = vma->obj;

		u32 old_read = obj->base.read_domains;

		u32 old_write = obj->base.write_domain;



		obj->base.write_domain = obj->base.pending_write_domain;

		if (obj->base.write_domain)
@@ -1329,7 +1327,6 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas, 


		i915_vma_move_to_active(vma, req, vma->exec_entry->flags);

		eb_export_fence(obj, req, vma->exec_entry->flags);

		trace_i915_gem_object_change_domain(obj, old_read, old_write);

	}

}

drivers/gpu/drm/i915/i915_trace.h

+0 −24
Original line number Diff line number Diff line
@@ -175,30 +175,6 @@ TRACE_EVENT(i915_vma_unbind, 
		      __entry->obj, __entry->offset, __entry->size, __entry->vm)

);



TRACE_EVENT(i915_gem_object_change_domain,

	    TP_PROTO(struct drm_i915_gem_object *obj, u32 old_read, u32 old_write),

	    TP_ARGS(obj, old_read, old_write),



	    TP_STRUCT__entry(

			     __field(struct drm_i915_gem_object *, obj)

			     __field(u32, read_domains)

			     __field(u32, write_domain)

			     ),



	    TP_fast_assign(

			   __entry->obj = obj;

			   __entry->read_domains = obj->base.read_domains | (old_read << 16);

			   __entry->write_domain = obj->base.write_domain | (old_write << 16);

			   ),



	    TP_printk("obj=%p, read=%02x=>%02x, write=%02x=>%02x",

		      __entry->obj,

		      __entry->read_domains >> 16,

		      __entry->read_domains & 0xffff,

		      __entry->write_domain >> 16,

		      __entry->write_domain & 0xffff)

);



TRACE_EVENT(i915_gem_object_pwrite,

	    TP_PROTO(struct drm_i915_gem_object *obj, u32 offset, u32 len),

	    TP_ARGS(obj, offset, len),