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Commit e47d034a authored by Satya Rama Aditya Pinapala's avatar Satya Rama Aditya Pinapala Committed by Gerrit - the friendly Code Review server
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dt-bindings: msm: Adding include files required for mdss compiling 



This change propogates files from 4.14 to 4.19 to fix compilation
for mdss pll.

Change-Id: I253277bb3b99dca94f69a3194bfb680f31297f05
Signed-off-by: default avatarSatya Rama Aditya Pinapala <psraditya30@codeaurora.org>
parent ea1d7b23

include/dt-bindings/clock/mdss-10nm-pll-clk.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 */



#ifndef __MDSS_10NM_PLL_CLK_H

#define __MDSS_10NM_PLL_CLK_H



/* DSI PLL clocks */

#define VCO_CLK_0		0

#define PLL_OUT_DIV_0_CLK	1

#define BITCLK_SRC_0_CLK	2

#define BYTECLK_SRC_0_CLK	3

#define POST_BIT_DIV_0_CLK	4

#define POST_VCO_DIV_0_CLK	5

#define BYTECLK_MUX_0_CLK	6

#define PCLK_SRC_MUX_0_CLK	7

#define PCLK_SRC_0_CLK		8

#define PCLK_MUX_0_CLK		9

#define VCO_CLK_1		10

#define PLL_OUT_DIV_1_CLK	11

#define BITCLK_SRC_1_CLK	12

#define BYTECLK_SRC_1_CLK	13

#define POST_BIT_DIV_1_CLK	14

#define POST_VCO_DIV_1_CLK	15

#define BYTECLK_MUX_1_CLK	16

#define PCLK_SRC_MUX_1_CLK	17

#define PCLK_SRC_1_CLK		18

#define PCLK_MUX_1_CLK		19



/* DP PLL clocks */

#define	DP_VCO_CLK	0

#define	DP_LINK_CLK_DIVSEL_TEN	1

#define	DP_VCO_DIVIDED_TWO_CLK_SRC	2

#define	DP_VCO_DIVIDED_FOUR_CLK_SRC	3

#define	DP_VCO_DIVIDED_SIX_CLK_SRC	4

#define	DP_VCO_DIVIDED_CLK_SRC_MUX	5

#endif

include/dt-bindings/clock/mdss-14nm-pll-clk.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2016,2018-2019, The Linux Foundation. All rights reserved.

 */



#ifndef __MDSS_14NM_PLL_CLK_H

#define __MDSS_14NM_PLL_CLK_H



/* DSI PLL clocks */

#define BYTE0_MUX_CLK             0

#define BYTE0_SRC_CLK             1

#define PIX0_MUX_CLK              2

#define PIX0_SRC_CLK              3

#define N2_DIV_0_CLK              4

#define POST_N1_DIV_0_CLK         5

#define VCO_CLK_0_CLK             6

#define SHADOW_BYTE0_SRC_CLK      7

#define SHADOW_PIX0_SRC_CLK       8

#define SHADOW_N2_DIV_0_CLK       9

#define SHADOW_POST_N1_DIV_0_CLK  10

#define SHADOW_VCO_CLK_0_CLK      11

#define BYTE1_MUX_CLK             12

#define BYTE1_SRC_CLK             13

#define PIX1_MUX_CLK              14

#define PIX1_SRC_CLK              15

#define N2_DIV_1_CLK              16

#define POST_N1_DIV_1_CLK         17

#define VCO_CLK_1_CLK             18

#define SHADOW_BYTE1_SRC_CLK      19

#define SHADOW_PIX1_SRC_CLK       20

#define SHADOW_N2_DIV_1_CLK       21

#define SHADOW_POST_N1_DIV_1_CLK  22

#define SHADOW_VCO_CLK_1_CLK      23



/* DP PLL clocks */

#define DP_VCO_CLK			0

#define DP_PHY_PLL_LINK_CLK		1

#define DP_VCO_DIVSEL_FOUR_CLK_SRC	2

#define DP_VCO_DIVSEL_TWO_CLK_SRC	3

#define DP_PHY_PLL_VCO_DIV_CLK		4



#endif

include/dt-bindings/clock/mdss-28nm-pll-clk.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 */



#ifndef __MDSS_28NM_PLL_CLK_H

#define __MDSS_28NM_PLL_CLK_H



/* DSI PLL clocks */

#define VCO_CLK_0		0

#define ANALOG_POSTDIV_0_CLK	1

#define INDIRECT_PATH_SRC_0_CLK	2

#define BYTECLK_SRC_MUX_0_CLK	3

#define BYTECLK_SRC_0_CLK	4

#define PCLK_SRC_0_CLK		5

#define VCO_CLK_1		6

#define ANALOG_POSTDIV_1_CLK	7

#define INDIRECT_PATH_SRC_1_CLK	8

#define BYTECLK_SRC_MUX_1_CLK	9

#define BYTECLK_SRC_1_CLK	10

#define PCLK_SRC_1_CLK		11



/* HDMI PLL clocks */

#define HDMI_VCO_CLK			0

#define HDMI_VCO_DIVIDED_1_CLK_SRC	1

#define HDMI_VCO_DIVIDED_TWO_CLK_SRC	2

#define HDMI_VCO_DIVIDED_FOUR_CLK_SRC	3

#define HDMI_VCO_DIVIDED_SIX_CLK_SRC	4

#define HDMI_PCLK_SRC_MUX		5

#define HDMI_PCLK_SRC			6

#endif