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Commit e3c71eb2 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/gr: namespace + nvidia gpu names (no binary change) 



The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 05c7145d

drivers/gpu/drm/nouveau/include/nvkm/core/os.h

+1 −0
Original line number Diff line number Diff line
@@ -250,5 +250,6 @@ 
#define nouveau_disp nvkm_disp

#define nouveau_fifo_chan nvkm_fifo_chan

#define nouveau_fifo nvkm_fifo

#define nouveau_gr nvkm_gr



#endif

drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h

+65 −65
Original line number Diff line number Diff line 
#ifndef __NOUVEAU_GR_H__

#define __NOUVEAU_GR_H__



#include <core/engine.h>

#ifndef __NVKM_GR_H__

#define __NVKM_GR_H__

#include <core/engctx.h>

#include <core/enum.h>



struct nouveau_gr_chan {

	struct nouveau_engctx base;

struct nvkm_gr_chan {

	struct nvkm_engctx base;

};



#define nouveau_gr_context_create(p,e,c,g,s,a,f,d)                          \

	nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))

#define nouveau_gr_context_destroy(d)                                       \

	nouveau_engctx_destroy(&(d)->base)

#define nouveau_gr_context_init(d)                                          \

	nouveau_engctx_init(&(d)->base)

#define nouveau_gr_context_fini(d,s)                                        \

	nouveau_engctx_fini(&(d)->base, (s))

#define nvkm_gr_context_create(p,e,c,g,s,a,f,d)                          \

	nvkm_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))

#define nvkm_gr_context_destroy(d)                                       \

	nvkm_engctx_destroy(&(d)->base)

#define nvkm_gr_context_init(d)                                          \

	nvkm_engctx_init(&(d)->base)

#define nvkm_gr_context_fini(d,s)                                        \

	nvkm_engctx_fini(&(d)->base, (s))



#define _nvkm_gr_context_dtor _nvkm_engctx_dtor

#define _nvkm_gr_context_init _nvkm_engctx_init

#define _nvkm_gr_context_fini _nvkm_engctx_fini

#define _nvkm_gr_context_rd32 _nvkm_engctx_rd32

#define _nvkm_gr_context_wr32 _nvkm_engctx_wr32



#define _nouveau_gr_context_dtor _nouveau_engctx_dtor

#define _nouveau_gr_context_init _nouveau_engctx_init

#define _nouveau_gr_context_fini _nouveau_engctx_fini

#define _nouveau_gr_context_rd32 _nouveau_engctx_rd32

#define _nouveau_gr_context_wr32 _nouveau_engctx_wr32

#include <core/engine.h>



struct nouveau_gr {

	struct nouveau_engine base;

struct nvkm_gr {

	struct nvkm_engine base;



	/* Returns chipset-specific counts of units packed into an u64.

	 */

	u64 (*units)(struct nouveau_gr *);

	u64 (*units)(struct nvkm_gr *);

};



static inline struct nouveau_gr *

nouveau_gr(void *obj)

static inline struct nvkm_gr *

nvkm_gr(void *obj)

{

	return (void *)nouveau_engine(obj, NVDEV_ENGINE_GR);

	return (void *)nvkm_engine(obj, NVDEV_ENGINE_GR);

}



#define nouveau_gr_create(p,e,c,y,d)                                        \

	nouveau_engine_create((p), (e), (c), (y), "PGR", "graphics", (d))

#define nouveau_gr_destroy(d)                                               \

	nouveau_engine_destroy(&(d)->base)

#define nouveau_gr_init(d)                                                  \

	nouveau_engine_init(&(d)->base)

#define nouveau_gr_fini(d,s)                                                \

	nouveau_engine_fini(&(d)->base, (s))

#define nvkm_gr_create(p,e,c,y,d)                                        \

	nvkm_engine_create((p), (e), (c), (y), "PGR", "graphics", (d))

#define nvkm_gr_destroy(d)                                               \

	nvkm_engine_destroy(&(d)->base)

#define nvkm_gr_init(d)                                                  \

	nvkm_engine_init(&(d)->base)

#define nvkm_gr_fini(d,s)                                                \

	nvkm_engine_fini(&(d)->base, (s))



#define _nouveau_gr_dtor _nouveau_engine_dtor

#define _nouveau_gr_init _nouveau_engine_init

#define _nouveau_gr_fini _nouveau_engine_fini

#define _nvkm_gr_dtor _nvkm_engine_dtor

#define _nvkm_gr_init _nvkm_engine_init

#define _nvkm_gr_fini _nvkm_engine_fini



extern struct nouveau_oclass nv04_gr_oclass;

extern struct nouveau_oclass nv10_gr_oclass;

extern struct nouveau_oclass nv20_gr_oclass;

extern struct nouveau_oclass nv25_gr_oclass;

extern struct nouveau_oclass nv2a_gr_oclass;

extern struct nouveau_oclass nv30_gr_oclass;

extern struct nouveau_oclass nv34_gr_oclass;

extern struct nouveau_oclass nv35_gr_oclass;

extern struct nouveau_oclass nv40_gr_oclass;

extern struct nouveau_oclass nv50_gr_oclass;

extern struct nouveau_oclass *nvc0_gr_oclass;

extern struct nouveau_oclass *nvc1_gr_oclass;

extern struct nouveau_oclass *nvc4_gr_oclass;

extern struct nouveau_oclass *nvc8_gr_oclass;

extern struct nouveau_oclass *nvd7_gr_oclass;

extern struct nouveau_oclass *nvd9_gr_oclass;

extern struct nouveau_oclass *nve4_gr_oclass;

extern struct nouveau_oclass *gk20a_gr_oclass;

extern struct nouveau_oclass *nvf0_gr_oclass;

extern struct nouveau_oclass *gk110b_gr_oclass;

extern struct nouveau_oclass *nv108_gr_oclass;

extern struct nouveau_oclass *gm107_gr_oclass;

extern struct nvkm_oclass nv04_gr_oclass;

extern struct nvkm_oclass nv10_gr_oclass;

extern struct nvkm_oclass nv20_gr_oclass;

extern struct nvkm_oclass nv25_gr_oclass;

extern struct nvkm_oclass nv2a_gr_oclass;

extern struct nvkm_oclass nv30_gr_oclass;

extern struct nvkm_oclass nv34_gr_oclass;

extern struct nvkm_oclass nv35_gr_oclass;

extern struct nvkm_oclass nv40_gr_oclass;

extern struct nvkm_oclass nv50_gr_oclass;

extern struct nvkm_oclass *gf100_gr_oclass;

extern struct nvkm_oclass *gf108_gr_oclass;

extern struct nvkm_oclass *gf104_gr_oclass;

extern struct nvkm_oclass *gf110_gr_oclass;

extern struct nvkm_oclass *gf117_gr_oclass;

extern struct nvkm_oclass *gf119_gr_oclass;

extern struct nvkm_oclass *gk104_gr_oclass;

extern struct nvkm_oclass *gk20a_gr_oclass;

extern struct nvkm_oclass *gk110_gr_oclass;

extern struct nvkm_oclass *gk110b_gr_oclass;

extern struct nvkm_oclass *gk208_gr_oclass;

extern struct nvkm_oclass *gm107_gr_oclass;



extern const struct nouveau_bitfield nv04_gr_nsource[];

extern struct nouveau_ofuncs nv04_gr_ofuncs;

bool nv04_gr_idle(void *obj);

#include <core/enum.h>



extern const struct nouveau_bitfield nv10_gr_intr_name[];

extern const struct nouveau_bitfield nv10_gr_nstatus[];

extern const struct nvkm_bitfield nv04_gr_nsource[];

extern struct nvkm_ofuncs nv04_gr_ofuncs;

bool nv04_gr_idle(void *obj);



extern const struct nouveau_enum nv50_data_error_names[];

extern const struct nvkm_bitfield nv10_gr_intr_name[];

extern const struct nvkm_bitfield nv10_gr_nstatus[];



extern const struct nvkm_enum nv50_data_error_names[];

#endif

drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c

+9 −9
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc0_gr_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf100_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;

		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;

		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
@@ -116,7 +116,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;

		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;

		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
@@ -149,7 +149,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;

		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;

		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
@@ -181,7 +181,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;

		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;

		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
@@ -214,7 +214,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;

		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;

		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
@@ -246,7 +246,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc1_gr_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf108_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;

		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;

		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
@@ -278,7 +278,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc8_gr_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf110_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;

		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;

		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
@@ -311,7 +311,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvd9_gr_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf119_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;

		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;

		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
@@ -341,7 +341,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvd7_gr_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf117_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;

		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;

		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c

+6 −6
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_gr_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gk104_gr_oclass;

		device->oclass[NVDEV_ENGINE_DISP   ] =  gk104_disp_oclass;

		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;

		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
@@ -117,7 +117,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_gr_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gk104_gr_oclass;

		device->oclass[NVDEV_ENGINE_DISP   ] =  gk104_disp_oclass;

		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;

		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
@@ -151,7 +151,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_gr_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gk104_gr_oclass;

		device->oclass[NVDEV_ENGINE_DISP   ] =  gk104_disp_oclass;

		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;

		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
@@ -207,7 +207,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvf0_gr_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gk110_gr_oclass;

		device->oclass[NVDEV_ENGINE_DISP   ] =  gk110_disp_oclass;

		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;

		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
@@ -275,7 +275,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk208_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nv108_gr_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gk208_gr_oclass;

		device->oclass[NVDEV_ENGINE_DISP   ] =  gk110_disp_oclass;

		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;

		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
@@ -308,7 +308,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk208_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nv108_gr_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gk208_gr_oclass;

		device->oclass[NVDEV_ENGINE_DISP   ] =  gk110_disp_oclass;

		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;

		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild

+18 −18
Original line number Diff line number Diff line 
nvkm-y += nvkm/engine/gr/ctxnv40.o

nvkm-y += nvkm/engine/gr/ctxnv50.o

nvkm-y += nvkm/engine/gr/ctxnvc0.o

nvkm-y += nvkm/engine/gr/ctxnvc1.o

nvkm-y += nvkm/engine/gr/ctxnvc4.o

nvkm-y += nvkm/engine/gr/ctxnvc8.o

nvkm-y += nvkm/engine/gr/ctxnvd7.o

nvkm-y += nvkm/engine/gr/ctxnvd9.o

nvkm-y += nvkm/engine/gr/ctxnve4.o

nvkm-y += nvkm/engine/gr/ctxgf100.o

nvkm-y += nvkm/engine/gr/ctxgf108.o

nvkm-y += nvkm/engine/gr/ctxgf104.o

nvkm-y += nvkm/engine/gr/ctxgf110.o

nvkm-y += nvkm/engine/gr/ctxgf117.o

nvkm-y += nvkm/engine/gr/ctxgf119.o

nvkm-y += nvkm/engine/gr/ctxgk104.o

nvkm-y += nvkm/engine/gr/ctxgk20a.o

nvkm-y += nvkm/engine/gr/ctxnvf0.o

nvkm-y += nvkm/engine/gr/ctxgk110.o

nvkm-y += nvkm/engine/gr/ctxgk110b.o

nvkm-y += nvkm/engine/gr/ctxnv108.o

nvkm-y += nvkm/engine/gr/ctxgk208.o

nvkm-y += nvkm/engine/gr/ctxgm107.o

nvkm-y += nvkm/engine/gr/nv04.o

nvkm-y += nvkm/engine/gr/nv10.o
@@ -22,15 +22,15 @@ nvkm-y += nvkm/engine/gr/nv34.o 
nvkm-y += nvkm/engine/gr/nv35.o

nvkm-y += nvkm/engine/gr/nv40.o

nvkm-y += nvkm/engine/gr/nv50.o

nvkm-y += nvkm/engine/gr/nvc0.o

nvkm-y += nvkm/engine/gr/nvc1.o

nvkm-y += nvkm/engine/gr/nvc4.o

nvkm-y += nvkm/engine/gr/nvc8.o

nvkm-y += nvkm/engine/gr/nvd7.o

nvkm-y += nvkm/engine/gr/nvd9.o

nvkm-y += nvkm/engine/gr/nve4.o

nvkm-y += nvkm/engine/gr/gf100.o

nvkm-y += nvkm/engine/gr/gf108.o

nvkm-y += nvkm/engine/gr/gf104.o

nvkm-y += nvkm/engine/gr/gf110.o

nvkm-y += nvkm/engine/gr/gf117.o

nvkm-y += nvkm/engine/gr/gf119.o

nvkm-y += nvkm/engine/gr/gk104.o

nvkm-y += nvkm/engine/gr/gk20a.o

nvkm-y += nvkm/engine/gr/nvf0.o

nvkm-y += nvkm/engine/gr/gk110.o

nvkm-y += nvkm/engine/gr/gk110b.o

nvkm-y += nvkm/engine/gr/nv108.o

nvkm-y += nvkm/engine/gr/gk208.o

nvkm-y += nvkm/engine/gr/gm107.o