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Commit 05c7145d authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/fifo: namespace + nvidia gpu names (no binary change) 



The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 5b85057a

drivers/gpu/drm/nouveau/include/nvkm/core/os.h

+2 −0
Original line number Diff line number Diff line
@@ -248,5 +248,7 @@ 
#define nouveau_dmaeng nvkm_dmaeng

#define nouveau_dmaobj nvkm_dmaobj

#define nouveau_disp nvkm_disp

#define nouveau_fifo_chan nvkm_fifo_chan

#define nouveau_fifo nvkm_fifo



#endif

drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h

+86 −86
Original line number Diff line number Diff line 
#ifndef __NOUVEAU_FIFO_H__

#define __NOUVEAU_FIFO_H__



#ifndef __NVKM_FIFO_H__

#define __NVKM_FIFO_H__

#include <core/namedb.h>

#include <core/gpuobj.h>

#include <core/engine.h>

#include <core/event.h>



struct nouveau_fifo_chan {

	struct nouveau_namedb namedb;

	struct nouveau_dmaobj *pushdma;

	struct nouveau_gpuobj *pushgpu;

struct nvkm_fifo_chan {

	struct nvkm_namedb namedb;

	struct nvkm_dmaobj *pushdma;

	struct nvkm_gpuobj *pushgpu;

	void __iomem *user;

	u64 addr;

	u32 size;
@@ -17,110 +13,114 @@ struct nouveau_fifo_chan { 
	atomic_t refcnt; /* NV04_NVSW_SET_REF */

};



static inline struct nouveau_fifo_chan *

nouveau_fifo_chan(void *obj)

static inline struct nvkm_fifo_chan *

nvkm_fifo_chan(void *obj)

{

	return (void *)nv_namedb(obj);

}



#define nouveau_fifo_channel_create(p,e,c,b,a,s,n,m,d)                         \

	nouveau_fifo_channel_create_((p), (e), (c), (b), (a), (s), (n),        \

#define nvkm_fifo_channel_create(p,e,c,b,a,s,n,m,d)                         \

	nvkm_fifo_channel_create_((p), (e), (c), (b), (a), (s), (n),        \

				     (m), sizeof(**d), (void **)d)

#define nouveau_fifo_channel_init(p)                                           \

	nouveau_namedb_init(&(p)->namedb)

#define nouveau_fifo_channel_fini(p,s)                                         \

	nouveau_namedb_fini(&(p)->namedb, (s))



int  nouveau_fifo_channel_create_(struct nouveau_object *,

				  struct nouveau_object *,

				  struct nouveau_oclass *,

#define nvkm_fifo_channel_init(p)                                           \

	nvkm_namedb_init(&(p)->namedb)

#define nvkm_fifo_channel_fini(p,s)                                         \

	nvkm_namedb_fini(&(p)->namedb, (s))



int  nvkm_fifo_channel_create_(struct nvkm_object *,

				  struct nvkm_object *,

				  struct nvkm_oclass *,

				  int bar, u32 addr, u32 size, u32 push,

				  u64 engmask, int len, void **);

void nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *);

void nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *);



#define _nouveau_fifo_channel_init _nouveau_namedb_init

#define _nouveau_fifo_channel_fini _nouveau_namedb_fini

#define _nvkm_fifo_channel_init _nvkm_namedb_init

#define _nvkm_fifo_channel_fini _nvkm_namedb_fini



void _nouveau_fifo_channel_dtor(struct nouveau_object *);

int  _nouveau_fifo_channel_map(struct nouveau_object *, u64 *, u32 *);

u32  _nouveau_fifo_channel_rd32(struct nouveau_object *, u64);

void _nouveau_fifo_channel_wr32(struct nouveau_object *, u64, u32);

int  _nouveau_fifo_channel_ntfy(struct nouveau_object *, u32, struct nvkm_event **);

void _nvkm_fifo_channel_dtor(struct nvkm_object *);

int  _nvkm_fifo_channel_map(struct nvkm_object *, u64 *, u32 *);

u32  _nvkm_fifo_channel_rd32(struct nvkm_object *, u64);

void _nvkm_fifo_channel_wr32(struct nvkm_object *, u64, u32);

int  _nvkm_fifo_channel_ntfy(struct nvkm_object *, u32, struct nvkm_event **);



struct nouveau_fifo_base {

	struct nouveau_gpuobj gpuobj;

#include <core/gpuobj.h>



struct nvkm_fifo_base {

	struct nvkm_gpuobj gpuobj;

};



#define nouveau_fifo_context_create(p,e,c,g,s,a,f,d)                           \

	nouveau_gpuobj_create((p), (e), (c), 0, (g), (s), (a), (f), (d))

#define nouveau_fifo_context_destroy(p)                                        \

	nouveau_gpuobj_destroy(&(p)->gpuobj)

#define nouveau_fifo_context_init(p)                                           \

	nouveau_gpuobj_init(&(p)->gpuobj)

#define nouveau_fifo_context_fini(p,s)                                         \

	nouveau_gpuobj_fini(&(p)->gpuobj, (s))

#define nvkm_fifo_context_create(p,e,c,g,s,a,f,d)                           \

	nvkm_gpuobj_create((p), (e), (c), 0, (g), (s), (a), (f), (d))

#define nvkm_fifo_context_destroy(p)                                        \

	nvkm_gpuobj_destroy(&(p)->gpuobj)

#define nvkm_fifo_context_init(p)                                           \

	nvkm_gpuobj_init(&(p)->gpuobj)

#define nvkm_fifo_context_fini(p,s)                                         \

	nvkm_gpuobj_fini(&(p)->gpuobj, (s))



#define _nvkm_fifo_context_dtor _nvkm_gpuobj_dtor

#define _nvkm_fifo_context_init _nvkm_gpuobj_init

#define _nvkm_fifo_context_fini _nvkm_gpuobj_fini

#define _nvkm_fifo_context_rd32 _nvkm_gpuobj_rd32

#define _nvkm_fifo_context_wr32 _nvkm_gpuobj_wr32



#define _nouveau_fifo_context_dtor _nouveau_gpuobj_dtor

#define _nouveau_fifo_context_init _nouveau_gpuobj_init

#define _nouveau_fifo_context_fini _nouveau_gpuobj_fini

#define _nouveau_fifo_context_rd32 _nouveau_gpuobj_rd32

#define _nouveau_fifo_context_wr32 _nouveau_gpuobj_wr32

#include <core/engine.h>

#include <core/event.h>



struct nouveau_fifo {

	struct nouveau_engine base;

struct nvkm_fifo {

	struct nvkm_engine base;



	struct nvkm_event cevent; /* channel creation event */

	struct nvkm_event uevent; /* async user trigger */



	struct nouveau_object **channel;

	struct nvkm_object **channel;

	spinlock_t lock;

	u16 min;

	u16 max;



	int  (*chid)(struct nouveau_fifo *, struct nouveau_object *);

	void (*pause)(struct nouveau_fifo *, unsigned long *);

	void (*start)(struct nouveau_fifo *, unsigned long *);

	int  (*chid)(struct nvkm_fifo *, struct nvkm_object *);

	void (*pause)(struct nvkm_fifo *, unsigned long *);

	void (*start)(struct nvkm_fifo *, unsigned long *);

};



static inline struct nouveau_fifo *

nouveau_fifo(void *obj)

static inline struct nvkm_fifo *

nvkm_fifo(void *obj)

{

	return (void *)nouveau_engine(obj, NVDEV_ENGINE_FIFO);

	return (void *)nvkm_engine(obj, NVDEV_ENGINE_FIFO);

}



#define nouveau_fifo_create(o,e,c,fc,lc,d)                                     \

	nouveau_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d)

#define nouveau_fifo_init(p)                                                   \

	nouveau_engine_init(&(p)->base)

#define nouveau_fifo_fini(p,s)                                                 \

	nouveau_engine_fini(&(p)->base, (s))

#define nvkm_fifo_create(o,e,c,fc,lc,d)                                     \

	nvkm_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d)

#define nvkm_fifo_init(p)                                                   \

	nvkm_engine_init(&(p)->base)

#define nvkm_fifo_fini(p,s)                                                 \

	nvkm_engine_fini(&(p)->base, (s))



int nouveau_fifo_create_(struct nouveau_object *, struct nouveau_object *,

			 struct nouveau_oclass *, int min, int max,

int nvkm_fifo_create_(struct nvkm_object *, struct nvkm_object *,

			 struct nvkm_oclass *, int min, int max,

			 int size, void **);

void nouveau_fifo_destroy(struct nouveau_fifo *);

void nvkm_fifo_destroy(struct nvkm_fifo *);

const char *

nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid);



#define _nouveau_fifo_init _nouveau_engine_init

#define _nouveau_fifo_fini _nouveau_engine_fini



extern struct nouveau_oclass *nv04_fifo_oclass;

extern struct nouveau_oclass *nv10_fifo_oclass;

extern struct nouveau_oclass *nv17_fifo_oclass;

extern struct nouveau_oclass *nv40_fifo_oclass;

extern struct nouveau_oclass *nv50_fifo_oclass;

extern struct nouveau_oclass *nv84_fifo_oclass;

extern struct nouveau_oclass *nvc0_fifo_oclass;

extern struct nouveau_oclass *nve0_fifo_oclass;

extern struct nouveau_oclass *gk20a_fifo_oclass;

extern struct nouveau_oclass *nv108_fifo_oclass;



int  nouveau_fifo_uevent_ctor(struct nouveau_object *, void *, u32,

nvkm_client_name_for_fifo_chid(struct nvkm_fifo *fifo, u32 chid);



#define _nvkm_fifo_init _nvkm_engine_init

#define _nvkm_fifo_fini _nvkm_engine_fini



extern struct nvkm_oclass *nv04_fifo_oclass;

extern struct nvkm_oclass *nv10_fifo_oclass;

extern struct nvkm_oclass *nv17_fifo_oclass;

extern struct nvkm_oclass *nv40_fifo_oclass;

extern struct nvkm_oclass *nv50_fifo_oclass;

extern struct nvkm_oclass *g84_fifo_oclass;

extern struct nvkm_oclass *gf100_fifo_oclass;

extern struct nvkm_oclass *gk104_fifo_oclass;

extern struct nvkm_oclass *gk20a_fifo_oclass;

extern struct nvkm_oclass *gk208_fifo_oclass;



int  nvkm_fifo_uevent_ctor(struct nvkm_object *, void *, u32,

			   struct nvkm_notify *);

void nouveau_fifo_uevent(struct nouveau_fifo *);



void nv04_fifo_intr(struct nouveau_subdev *);

int  nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *);

void nvkm_fifo_uevent(struct nvkm_fifo *);



void nv04_fifo_intr(struct nvkm_subdev *);

int  nv04_fifo_context_attach(struct nvkm_object *, struct nvkm_object *);

#endif

drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c

+2 −2
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ gm100_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

#endif

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk208_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_gr_oclass;

		device->oclass[NVDEV_ENGINE_DISP   ] =  gm107_disp_oclass;
@@ -128,7 +128,7 @@ gm100_identify(struct nouveau_device *device) 
#endif

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

#if 0

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk208_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_gr_oclass;

#endif

drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c

+13 −13
Original line number Diff line number Diff line
@@ -106,7 +106,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
@@ -135,7 +135,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
@@ -164,7 +164,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
@@ -193,7 +193,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
@@ -222,7 +222,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
@@ -251,7 +251,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
@@ -280,7 +280,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
@@ -309,7 +309,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
@@ -338,7 +338,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
@@ -368,7 +368,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gt215_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
@@ -399,7 +399,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gt215_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
@@ -429,7 +429,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gt215_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
@@ -459,7 +459,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gt215_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c

+9 −9
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc0_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
@@ -114,7 +114,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
@@ -147,7 +147,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
@@ -179,7 +179,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
@@ -212,7 +212,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
@@ -244,7 +244,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc1_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
@@ -276,7 +276,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc8_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
@@ -309,7 +309,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf110_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvd9_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
@@ -339,7 +339,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &gf100_bar_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvd7_gr_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;