Merge "disp: msm: dsi: add support to set continuous clock through phy" (e2be37e0) · Commits · e / devices / android_kernel_fairphone_FP4

msm/dsi/dsi_display.c

+13 −1

Original line number	Diff line number	Diff line
		@@ -984,7 +984,19 @@ static void _dsi_display_continuous_clk_ctrl(struct dsi_display *display,

		display_for_each_ctrl(i, display) {
		ctrl = &display->ctrl[i];

		/*
		* For phy ver 4.0 chipsets, configure DSI controller and
		* DSI PHY to force clk lane to HS mode always whereas
		* for other phy ver chipsets, configure DSI controller only.
		*/
		if (ctrl->phy->hw.ops.set_continuous_clk) {
		dsi_ctrl_hs_req_sel(ctrl->ctrl, true);
		dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
		dsi_phy_set_continuous_clk(ctrl->phy, enable);
		} else {
		dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
		}
		}
		}