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Commit a1b280db authored by Ritesh Kumar's avatar Ritesh Kumar
Browse files

disp: msm: dsi: add support to set continuous clock through phy 



For phy ver 4.0 chipsets, configure DSI controller and DSI PHY to
force clk lane to HS mode always. This change was missed while
propagating from 4.14 to 4.19.

Change-Id: I60370034f7b9ed5d036d9d22f0807250afbcbcd5
Signed-off-by: default avatarRitesh Kumar <riteshk@codeaurora.org>
parent 4fbdc645

msm/dsi/dsi_display.c

+13 −1
Original line number Diff line number Diff line
@@ -984,7 +984,19 @@ static void _dsi_display_continuous_clk_ctrl(struct dsi_display *display, 


	display_for_each_ctrl(i, display) {

		ctrl = &display->ctrl[i];



		/*

		 * For phy ver 4.0 chipsets, configure DSI controller and

		 * DSI PHY to force clk lane to HS mode always whereas

		 * for other phy ver chipsets, configure DSI controller only.

		 */

		if (ctrl->phy->hw.ops.set_continuous_clk) {

			dsi_ctrl_hs_req_sel(ctrl->ctrl, true);

			dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);

			dsi_phy_set_continuous_clk(ctrl->phy, enable);

		} else {

			dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);

		}

	}

}