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Commit dbb58d0f authored by Kefeng Wang's avatar Kefeng Wang Committed by Wei Xu
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arm64: dts: hip05: Add L2 cache topology



The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus
share one L2 cache, add them to the dtsi file so that the cache
hierarchy can be probed.

Signed-off-by: default avatarKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: default avatarWei Xu <xuwei5@hisilicon.com>
parent 92e963f5
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