usb: dwc3: Issue core soft reset upon controller halt failure

In case of composition switch there is a possibility of run/stop
bit gets cleared in the middle of a control transfer. If controller
has cached a SETUP packet but not yet written it to ep0 TRB, controller
halt fails even if there are no pending events in event ring. As part of
pull up enable run/stop bit gets set and control transfer starts, due to
that controller writes cached SETUP packet to ep0 TRB and triggers xfer
completion. Since run/stop bit is set Host issues bus reset and end
transfer and Halt are issued on ep0 because ep0 is not in SETUP phase.
However this does not recover the controller's ep0 state machine. As a
result controller is unable to handle SET ADDRESS SETUP packet issued by
host.

Before completing data stage of control transfer if vbus disconnects
controller halt fails even after issuing end transfer cmd on ep0 IN.
There is a possibility of race between controller accessing the ep0
buffer from cached TRB which was queued in data stage of control
transfer and end xfer command completion. This is resulting into
accessing of TRB buffer after controller halt failure by this time
buffer is already unmapped by dwc3_remove_requests().

Fix above issues by issuing core soft reset if control halt fails to
prevent controller from accessing cached TRB buffer. Also move issuing
of end xfer command for ep0 IN before un-mapping the ep0 TRB buffer in
case ep0 state is not in SETUP phase in dwc3_remove_requests().

Change-Id: Ie159e06a2537afcc9deee3f6670aac5d66b97b90
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Signed-off-by: Elson Roy Serrao <eserrao@codeaurora.org>