Merge "ARM: dts: msm: scuba: Add qcrypto node"

		hyplog-size-offset = <0x414>;

	};

	qcom_cedev: qcedev@1b20000 {

		compatible = "qcom,qcedev";

		reg = <0x1b20000 0x20000>,

			<0x1b04000 0x24000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;

		qcom,bam-pipe-pair = <3>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		qcom,ce-hw-shared;

		qcom,bam-ee = <0>;

		qcom,msm-bus,name = "qcedev-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<MSM_BUS_MASTER_CRYPTO_CORE0

				MSM_BUS_SLAVE_FIRST 0 0>,

				<MSM_BUS_MASTER_CRYPTO_CORE0

				MSM_BUS_SLAVE_FIRST 393600 393600>;

		clock-names =

			"core_clk_src", "core_clk",

			"iface_clk", "bus_clk";

		clocks =

			<&rpmcc QCEDEV_CE1_CLK>,

			<&rpmcc QCEDEV_CE1_CLK>,

			<&rpmcc QCEDEV_CE1_CLK>,

			<&rpmcc QCEDEV_CE1_CLK>;

		qcom,ce-opp-freq = <192000000>;

		qcom,smmu-s1-enable;

		iommus = <&apps_smmu 0x0086 0x0011>,

			 <&apps_smmu 0x0096 0x0011>;

		qcom,iommu-dma = "atomic";

		qcom_cedev_ns_cb {

			compatible = "qcom,qcedev,context-bank";

			label = "ns_context";

			iommus = <&apps_smmu 0x92 0>,

				<&apps_smmu 0x98 0x1>,

				<&apps_smmu 0x9F 0>;

		};

		qcom_cedev_s_cb {

			compatible = "qcom,qcedev,context-bank";

			label = "secure_context";

			iommus = <&apps_smmu 0x93 0>,

				<&apps_smmu 0x9C 0x1>,

				<&apps_smmu 0x9E 0>;

			qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */

			qcom,secure-context-bank;

		};

	};

	qcom_crypto: qcrypto@1b20000 {

		compatible = "qcom,qcrypto";

		reg = <0x1b20000 0x20000>,

			<0x1b04000 0x24000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;

		qcom,bam-pipe-pair = <2>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		qcom,bam-ee = <0>;

		qcom,ce-hw-shared;

		qcom,clk-mgmt-sus-res;

		qcom,msm-bus,name = "qcrypto-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<MSM_BUS_MASTER_CRYPTO_CORE0

			MSM_BUS_SLAVE_FIRST

			0 0>,

			<MSM_BUS_MASTER_CRYPTO_CORE0

			MSM_BUS_SLAVE_FIRST

			393600 393600>;

		clock-names =

			"core_clk_src", "core_clk",

			"iface_clk", "bus_clk";

		clocks =

			<&rpmcc QCRYPTO_CE1_CLK>,

			<&rpmcc QCRYPTO_CE1_CLK>,

			<&rpmcc QCRYPTO_CE1_CLK>,

			<&rpmcc QCRYPTO_CE1_CLK>;

		qcom,use-sw-aes-cbc-ecb-ctr-algo;

		qcom,use-sw-aes-xts-algo;

		qcom,use-sw-aes-ccm-algo;

		qcom,use-sw-ahash-algo;

		qcom,use-sw-aead-algo;

		qcom,use-sw-hmac-algo;

		qcom,smmu-s1-enable;

		iommus = <&apps_smmu 0x0084 0x0011>,

			<&apps_smmu 0x0094 0x0011>;

		qcom,iommu-dma = "atomic";

	};

	qcom,mpm2-sleep-counter@4403000 {

		compatible = "qcom,mpm2-sleep-counter";

		reg = <0x4403000 0x1000>;