Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d34c6d8a authored by Hugo Villeneuve's avatar Hugo Villeneuve Committed by Greg Kroah-Hartman
Browse files

serial: max310x: improve crystal stable clock detection 



commit 93cd256ab224c2519e7c4e5f58bb4f1ac2bf0965 upstream.

Some people are seeing a warning similar to this when using a crystal:

    max310x 11-006c: clock is not stable yet

The datasheet doesn't mention the maximum time to wait for the clock to be
stable when using a crystal, and it seems that the 10ms delay in the driver
is not always sufficient.

Jan Kundrát reported that it took three tries (each separated by 10ms) to
get a stable clock.

Modify behavior to check stable clock ready bit multiple times (20), and
waiting 10ms between each try.

Note: the first draft of the driver originally used a 50ms delay, without
checking the clock stable bit.
Then a loop with 1000 retries was implemented, each time reading the clock
stable bit.

Fixes: 4cf9a888 ("serial: max310x: Check the clock readiness")
Cc: stable@vger.kernel.org
Suggested-by: default avatarJan Kundrát <jan.kundrat@cesnet.cz>
Link: https://www.spinics.net/lists/linux-serial/msg35773.html
Link: https://lore.kernel.org/all/20240110174015.6f20195fde08e5c9e64e5675@hugovil.com/raw
Link: https://github.com/boundarydevices/linux/commit/e5dfe3e4a751392515d78051973190301a37ca9a


Signed-off-by: default avatarHugo Villeneuve <hvilleneuve@dimonoff.com>
Link: https://lore.kernel.org/r/20240116213001.3691629-3-hugo@hugovil.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 1b766291

drivers/tty/serial/max310x.c

+16 −5
Original line number Diff line number Diff line
@@ -235,6 +235,10 @@ 
#define MAX310x_REV_MASK		(0xf8)

#define MAX310X_WRITE_BIT		0x80



/* Crystal-related definitions */

#define MAX310X_XTAL_WAIT_RETRIES	20 /* Number of retries */

#define MAX310X_XTAL_WAIT_DELAY_MS	10 /* Delay between retries */



/* MAX3107 specific */

#define MAX3107_REV_ID			(0xa0)
@@ -600,13 +604,20 @@ static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s, 


	/* Wait for crystal */

	if (xtal) {

		unsigned int val = 0;

		msleep(10);

		bool stable = false;

		unsigned int try = 0, val = 0;



		do {

			msleep(MAX310X_XTAL_WAIT_DELAY_MS);

			regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val);

		if (!(val & MAX310X_STS_CLKREADY_BIT)) {



			if (val & MAX310X_STS_CLKREADY_BIT)

				stable = true;

		} while (!stable && (++try < MAX310X_XTAL_WAIT_RETRIES));



		if (!stable)

			dev_warn(dev, "clock is not stable yet\n");

	}

	}



	return (int)bestfreq;

}