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Commit d331328d authored by Andre Przywara's avatar Andre Przywara Committed by Maxime Ripard
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clk: sunxi: Improve divs_clk error handling and reporting



We catch errors in the base clock registration, failure to ioremap
and failures in the final of_clk_add_provider() call.
Also we unmap the registers when we need to rollback.

Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent b26803eb
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