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Commit d2eeeff8 authored by Satya Rama Aditya Pinapala's avatar Satya Rama Aditya Pinapala
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clk/qcom/mdss: Phy and PLL settings for Kona DSI 



This change updates Phy and PLL settings for DSI bring up on Kona.

Change-Id: I37b6670fc3c8b68943926882f4d42bc7e5de8c9b
Signed-off-by: default avatarSatya Rama Aditya Pinapala <psraditya30@codeaurora.org>
parent 9cec3b40

drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c

+3 −3
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 */



#define pr_fmt(fmt)	"%s: " fmt, __func__
@@ -1417,7 +1417,7 @@ static struct regmap_bus mdss_mux_regmap_bus = { 


static struct dsi_pll_vco_clk dsi0pll_vco_clk = {

	.ref_clk_rate = 19200000UL,

	.min_rate = 1000000000UL,

	.min_rate = 1500000000UL,

	.max_rate = 3500000000UL,

	.hw.init = &(struct clk_init_data){

			.name = "dsi0pll_vco_clk",
@@ -1430,7 +1430,7 @@ static struct dsi_pll_vco_clk dsi0pll_vco_clk = { 


static struct dsi_pll_vco_clk dsi1pll_vco_clk = {

	.ref_clk_rate = 19200000UL,

	.min_rate = 1000000000UL,

	.min_rate = 1500000000UL,

	.max_rate = 3500000000UL,

	.hw.init = &(struct clk_init_data){

			.name = "dsi1pll_vco_clk",

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c

+1 −0
Original line number Diff line number Diff line
@@ -271,6 +271,7 @@ int dsi_catalog_phy_setup(struct dsi_phy_hw *phy, 
	}



	phy->index = index;

	phy->version = version;

	set_bit(DSI_PHY_DPHY, phy->feature_map);



	dsi_phy_timing_calc_init(phy, version);

drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c

+12 −6
Original line number Diff line number Diff line
@@ -174,12 +174,18 @@ void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy, 
		return;

	}



	if (phy->version == DSI_PHY_VERSION_4_1) {

		vreg_ctrl_0 = 0x58;

		glbl_str_swi_cal_sel_ctrl = 0x00;

		glbl_hstx_str_ctrl_0 = 0x88;

	} else {

		/* Alter PHY configurations if data rate less than 1.5GHZ*/

		if (cfg->bit_clk_rate_hz < 1500000000)

			less_than_1500_mhz = true;

		vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;

		glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;

		glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;

	}



	/* de-assert digital and pll power down */

	data = BIT(6) | BIT(5);