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Commit cde7beeb authored by Manaf Meethalavalappu Pallikunhi's avatar Manaf Meethalavalappu Pallikunhi Committed by Gerrit - the friendly Code Review server
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ARM: dts: qcom: Add LMH-DCVSh configuration for LAGOON 

Add LMH-DCVSh device configuration like debug interrupt and cluster
affinity value for LAGOON. Add the CPU to LMH-DCVSh hardware mapping,
monitor LMH DCVSh interrupts and notify throttling information to
scheduler, along with the LMH thermal zone definition.

Change-Id: I51e7afd6f69c22e818d132a6f3c2a3055edfb7e3
parent df2b2496

qcom/lagoon-thermal.dtsi

+18 −0
Original line number Diff line number Diff line
@@ -45,6 +45,24 @@ 
			#cooling-cells = <2>;

		};

	};



	lmh_dcvs0: qcom,limits-dcvs@18358800 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <0>;

		reg = <0x18358800 0x1000>,

			<0x18323000 0x1000>;

		qcom,no-cooling-device-register;

	};



	lmh_dcvs1: qcom,limits-dcvs@18350800 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <1>;

		reg = <0x18350800 0x1000>,

			<0x18325800 0x1000>;

		qcom,no-cooling-device-register;

	};

};



&thermal_zones {

qcom/lagoon.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ 
			qcom,freq-domain = <&cpufreq_hw 0 6>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";
@@ -85,6 +86,7 @@ 
			qcom,freq-domain = <&cpufreq_hw 0 6>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_100>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_100: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;
@@ -117,6 +119,7 @@ 
			qcom,freq-domain = <&cpufreq_hw 0 6>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_200>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_200: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;
@@ -149,6 +152,7 @@ 
			qcom,freq-domain = <&cpufreq_hw 0 6>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_300>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_300: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;
@@ -182,6 +186,7 @@ 
			qcom,freq-domain = <&cpufreq_hw 0 6>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_400>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_400: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;
@@ -214,6 +219,7 @@ 
			qcom,freq-domain = <&cpufreq_hw 0 6>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_500>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_500: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;
@@ -246,6 +252,7 @@ 
			qcom,freq-domain = <&cpufreq_hw 1 2>;

			cache-size = <0x10000>;

			next-level-cache = <&L2_600>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			#cooling-cells = <2>;

			L2_600: l2-cache {

				compatible = "arm,arch-cache";
@@ -288,6 +295,7 @@ 
			qcom,freq-domain = <&cpufreq_hw 1 2>;

			cache-size = <0x10000>;

			next-level-cache = <&L2_700>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			L2_700: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x40000>;