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Commit cd9787e8 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'tegra-for-4.16-arm64-dt' of... 

Merge tag 'tegra-for-4.16-arm64-dt' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt

Pull "arm64: tegra: Changes for v4.16-rc1" from Thierry Reding:

This set of patches enables a bunch of new features on Jetson TX2 that
were finally unblocked by the GPIO driver getting merged for v4.15.

* tag 'tegra-for-4.16-arm64-dt' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Use sor1_out clock
  arm64: tegra: Fix SD write-protect polarity on Jetson TX2
  arm64: tegra: Add CPU and PSCI nodes for NVIDIA Tegra210 platforms
  arm64: tegra: Enable HDMI on Jetson TX2
  arm64: tegra: Mark I2C4 as DDC on P3310
  arm64: tegra: Add display nodes on Tegra186
  arm64: tegra: Add SMMU node for Tegra186
  arm64: tegra: Enable memory controller on P3310
  arm64: tegra: Add memory controller on Tegra186
  arm64: tegra: Add FUSE block on Tegra186
  arm64: tegra: Add MISC registers on Tegra186
parents fe132d1a 50f5b841

arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts

+51 −0
Original line number Diff line number Diff line
@@ -74,6 +74,43 @@ 
		};

	};



	host1x@13e00000 {

		status = "okay";



		dpaux@15040000 {

			status = "okay";

		};



		display-hub@15200000 {

			status = "okay";

		};



		dsi@15300000 {

			status = "disabled";

		};



		sor@15540000 {

			status = "disabled";



			nvidia,dpaux = <&dpaux1>;

		};



		sor@15580000 {

			status = "okay";



			avdd-io-supply = <&vdd_hdmi_1v05>;

			vdd-pll-supply = <&vdd_1v8_ap>;

			hdmi-supply = <&vdd_hdmi>;



			nvidia,ddc-i2c-bus = <&ddc>;

			nvidia,hpd-gpio = <&gpio TEGRA_MAIN_GPIO(P, 1) GPIO_ACTIVE_LOW>;

		};



		dpaux@155c0000 {

			status = "okay";

		};

	};



	gpio-keys {

		compatible = "gpio-keys";
@@ -120,5 +157,19 @@ 


			vin-supply = <&vdd_3v3_sys>;

		};



		vdd_hdmi: regulator@101 {

			compatible = "regulator-fixed";

			reg = <101>;



			regulator-name = "VDD_HDMI_5V0";

			regulator-min-microvolt = <5000000>;

			regulator-max-microvolt = <5000000>;



			gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;

			enable-active-high;



			vin-supply = <&vdd_5v0_sys>;

		};

	};

};

arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi

+7 −3
Original line number Diff line number Diff line
@@ -51,6 +51,10 @@ 
		};

	};



	memory-controller@2c00000 {

		status = "okay";

	};



	serial@3100000 {

		status = "okay";

	};
@@ -73,7 +77,7 @@ 
		status = "okay";

	};



	i2c@3190000 {

	ddc: i2c@3190000 {

		status = "okay";

	};
@@ -88,7 +92,7 @@ 
	/* SDMMC1 (SD/MMC) */

	sdhci@3400000 {

		cd-gpios = <&gpio TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>;

		wp-gpios = <&gpio TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_LOW>;

		wp-gpios = <&gpio TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>;



		vqmmc-supply = <&vddio_sdmmc1>;

	};
@@ -317,7 +321,7 @@ 
						regulator-max-microvolt = <2800000>;

					};



					avdd_1v05: ldo7 {

					vdd_hdmi_1v05: ldo7 {

						regulator-name = "VDD_HDMI_1V05";

						regulator-min-microvolt = <1050000>;

						regulator-max-microvolt = <1050000>;

arch/arm64/boot/dts/nvidia/tegra186.dtsi

+351 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
#include <dt-bindings/gpio/tegra186-gpio.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/mailbox/tegra186-hsp.h>

#include <dt-bindings/memory/tegra186-mc.h>

#include <dt-bindings/power/tegra186-powergate.h>

#include <dt-bindings/reset/tegra186-reset.h>

#include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
@@ -13,6 +14,12 @@ 
	#address-cells = <2>;

	#size-cells = <2>;



	misc@100000 {

		compatible = "nvidia,tegra186-misc";

		reg = <0x0 0x00100000 0x0 0xf000>,

		      <0x0 0x0010f000 0x0 0x1000>;

	};



	gpio: gpio@2200000 {

		compatible = "nvidia,tegra186-gpio";

		reg-names = "security", "gpio";
@@ -61,6 +68,12 @@ 
		snps,rxpbl = <8>;

	};



	memory-controller@2c00000 {

		compatible = "nvidia,tegra186-mc";

		reg = <0x0 0x02c00000 0x0 0xb0000>;

		status = "disabled";

	};



	uarta: serial@3100000 {

		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";

		reg = <0x0 0x03100000 0x0 0x40>;
@@ -259,6 +272,13 @@ 
		status = "disabled";

	};



	fuse@3820000 {

		compatible = "nvidia,tegra186-efuse";

		reg = <0x0 0x03820000 0x0 0x10000>;

		clocks = <&bpmp TEGRA186_CLK_FUSE>;

		clock-names = "fuse";

	};



	gic: interrupt-controller@3881000 {

		compatible = "arm,gic-400";

		#interrupt-cells = <3>;
@@ -437,6 +457,79 @@ 
		};

	};



	smmu: iommu@12000000 {

		compatible = "arm,mmu-500";

		reg = <0 0x12000000 0 0x800000>;

		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;

		stream-match-mask = <0x7f80>;

		#global-interrupts = <1>;

		#iommu-cells = <1>;

	};



	host1x@13e00000 {

		compatible = "nvidia,tegra186-host1x", "simple-bus";

		reg = <0x0 0x13e00000 0x0 0x10000>,
@@ -453,6 +546,129 @@ 
		#size-cells = <1>;



		ranges = <0x15000000 0x0 0x15000000 0x01000000>;

		iommus = <&smmu TEGRA186_SID_HOST1X>;



		dpaux1: dpaux@15040000 {

			compatible = "nvidia,tegra186-dpaux";

			reg = <0x15040000 0x10000>;

			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA186_CLK_DPAUX1>,

				 <&bpmp TEGRA186_CLK_PLLDP>;

			clock-names = "dpaux", "parent";

			resets = <&bpmp TEGRA186_RESET_DPAUX1>;

			reset-names = "dpaux";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;



			state_dpaux1_aux: pinmux-aux {

				groups = "dpaux-io";

				function = "aux";

			};



			state_dpaux1_i2c: pinmux-i2c {

				groups = "dpaux-io";

				function = "i2c";

			};



			state_dpaux1_off: pinmux-off {

				groups = "dpaux-io";

				function = "off";

			};



			i2c-bus {

				#address-cells = <1>;

				#size-cells = <0>;

			};

		};



		display-hub@15200000 {

			compatible = "nvidia,tegra186-display", "simple-bus";

			resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,

				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,

				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,

				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,

				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,

				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,

				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;

			reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",

				      "wgrp3", "wgrp4", "wgrp5";

			clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,

				 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,

				 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;

			clock-names = "disp", "dsc", "hub";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;



			#address-cells = <1>;

			#size-cells = <1>;



			ranges = <0x15200000 0x15200000 0x40000>;



			display@15200000 {

				compatible = "nvidia,tegra186-dc";

				reg = <0x15200000 0x10000>;

				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;

				clock-names = "dc";

				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;

				reset-names = "dc";



				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;



				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;

				nvidia,head = <0>;

			};



			display@15210000 {

				compatible = "nvidia,tegra186-dc";

				reg = <0x15210000 0x10000>;

				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;

				clock-names = "dc";

				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;

				reset-names = "dc";



				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;

				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;



				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;

				nvidia,head = <1>;

			};



			display@15220000 {

				compatible = "nvidia,tegra186-dc";

				reg = <0x15220000 0x10000>;

				interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;

				clock-names = "dc";

				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;

				reset-names = "dc";



				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;

				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;



				nvidia,outputs = <&sor0 &sor1>;

				nvidia,head = <2>;

			};

		};



		dsia: dsi@15300000 {

			compatible = "nvidia,tegra186-dsi";

			reg = <0x15300000 0x10000>;

			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA186_CLK_DSI>,

				 <&bpmp TEGRA186_CLK_DSIA_LP>,

				 <&bpmp TEGRA186_CLK_PLLD>;

			clock-names = "dsi", "lp", "parent";

			resets = <&bpmp TEGRA186_RESET_DSI>;

			reset-names = "dsi";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

		};



		vic@15340000 {

			compatible = "nvidia,tegra186-vic";
@@ -465,6 +681,141 @@ 


			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;

		};



		dsib: dsi@15400000 {

			compatible = "nvidia,tegra186-dsi";

			reg = <0x15400000 0x10000>;

			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA186_CLK_DSIB>,

				 <&bpmp TEGRA186_CLK_DSIB_LP>,

				 <&bpmp TEGRA186_CLK_PLLD>;

			clock-names = "dsi", "lp", "parent";

			resets = <&bpmp TEGRA186_RESET_DSIB>;

			reset-names = "dsi";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

		};



		sor0: sor@15540000 {

			compatible = "nvidia,tegra186-sor";

			reg = <0x15540000 0x10000>;

			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA186_CLK_SOR0>,

				 <&bpmp TEGRA186_CLK_SOR0_OUT>,

				 <&bpmp TEGRA186_CLK_PLLD2>,

				 <&bpmp TEGRA186_CLK_PLLDP>,

				 <&bpmp TEGRA186_CLK_SOR_SAFE>,

				 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;

			clock-names = "sor", "out", "parent", "dp", "safe",

				      "pad";

			resets = <&bpmp TEGRA186_RESET_SOR0>;

			reset-names = "sor";

			pinctrl-0 = <&state_dpaux_aux>;

			pinctrl-1 = <&state_dpaux_i2c>;

			pinctrl-2 = <&state_dpaux_off>;

			pinctrl-names = "aux", "i2c", "off";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

			nvidia,interface = <0>;

		};



		sor1: sor@15580000 {

			compatible = "nvidia,tegra186-sor1";

			reg = <0x15580000 0x10000>;

			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA186_CLK_SOR1>,

				 <&bpmp TEGRA186_CLK_SOR1_OUT>,

				 <&bpmp TEGRA186_CLK_PLLD3>,

				 <&bpmp TEGRA186_CLK_PLLDP>,

				 <&bpmp TEGRA186_CLK_SOR_SAFE>,

				 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;

			clock-names = "sor", "out", "parent", "dp", "safe",

				      "pad";

			resets = <&bpmp TEGRA186_RESET_SOR1>;

			reset-names = "sor";

			pinctrl-0 = <&state_dpaux1_aux>;

			pinctrl-1 = <&state_dpaux1_i2c>;

			pinctrl-2 = <&state_dpaux1_off>;

			pinctrl-names = "aux", "i2c", "off";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

			nvidia,interface = <1>;

		};



		dpaux: dpaux@155c0000 {

			compatible = "nvidia,tegra186-dpaux";

			reg = <0x155c0000 0x10000>;

			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA186_CLK_DPAUX>,

				 <&bpmp TEGRA186_CLK_PLLDP>;

			clock-names = "dpaux", "parent";

			resets = <&bpmp TEGRA186_RESET_DPAUX>;

			reset-names = "dpaux";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;



			state_dpaux_aux: pinmux-aux {

				groups = "dpaux-io";

				function = "aux";

			};



			state_dpaux_i2c: pinmux-i2c {

				groups = "dpaux-io";

				function = "i2c";

			};



			state_dpaux_off: pinmux-off {

				groups = "dpaux-io";

				function = "off";

			};



			i2c-bus {

				#address-cells = <1>;

				#size-cells = <0>;

			};

		};



		padctl@15880000 {

			compatible = "nvidia,tegra186-dsi-padctl";

			reg = <0x15880000 0x10000>;

			resets = <&bpmp TEGRA186_RESET_DSI>;

			reset-names = "dsi";

			status = "disabled";

		};



		dsic: dsi@15900000 {

			compatible = "nvidia,tegra186-dsi";

			reg = <0x15900000 0x10000>;

			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA186_CLK_DSIC>,

				 <&bpmp TEGRA186_CLK_DSIC_LP>,

				 <&bpmp TEGRA186_CLK_PLLD>;

			clock-names = "dsi", "lp", "parent";

			resets = <&bpmp TEGRA186_RESET_DSIC>;

			reset-names = "dsi";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

		};



		dsid: dsi@15940000 {

			compatible = "nvidia,tegra186-dsi";

			reg = <0x15940000 0x10000>;

			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA186_CLK_DSID>,

				 <&bpmp TEGRA186_CLK_DSID_LP>,

				 <&bpmp TEGRA186_CLK_PLLD>;

			clock-names = "dsi", "lp", "parent";

			resets = <&bpmp TEGRA186_RESET_DSID>;

			reset-names = "dsi";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

		};

	};



	gpu@17000000 {

arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi

+23 −0
Original line number Diff line number Diff line
@@ -297,6 +297,29 @@ 
		};

	};



	cpus {

		cpu@0 {

			enable-method = "psci";

		};



		cpu@1 {

			enable-method = "psci";

		};



		cpu@2 {

			enable-method = "psci";

		};



		cpu@3 {

			enable-method = "psci";

		};

	};



	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};



	regulators {

		vdd_gpu: regulator@100 {

			compatible = "pwm-regulator";

arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi

+23 −0
Original line number Diff line number Diff line
@@ -52,4 +52,27 @@ 
			clock-frequency = <32768>;

		};

	};



	cpus {

		cpu@0 {

			enable-method = "psci";

		};



		cpu@1 {

			enable-method = "psci";

		};



		cpu@2 {

			enable-method = "psci";

		};



		cpu@3 {

			enable-method = "psci";

		};

	};



	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};

};