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Commit cc8dbbb4 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: add dpm support for CI dGPUs (v2) 



This adds dpm support for btc asics. This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen switching

Set radeon.dpm=1 to enable.

v2: remove unused radeon_atombios.c changes,
    make missing smc ucode non-fatal

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 41a524ab

drivers/gpu/drm/radeon/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -79,7 +79,8 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ 
	si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \

	r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \

	rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \

	trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o

	trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o ci_smc.o \

	ci_dpm.o



radeon-$(CONFIG_COMPAT) += radeon_ioc32.o

radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o

drivers/gpu/drm/radeon/ci_dpm.c

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+5006 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/radeon/ci_dpm.h

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+331 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2013 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef __CI_DPM_H__

#define __CI_DPM_H__



#include "ppsmc.h"



#define SMU__NUM_SCLK_DPM_STATE  8

#define SMU__NUM_MCLK_DPM_LEVELS 6

#define SMU__NUM_LCLK_DPM_LEVELS 8

#define SMU__NUM_PCIE_DPM_LEVELS 8

#include "smu7_discrete.h"



#define CISLANDS_MAX_HARDWARE_POWERLEVELS 2



struct ci_pl {

	u32 mclk;

	u32 sclk;

	enum radeon_pcie_gen pcie_gen;

	u16 pcie_lane;

};



struct ci_ps {

	u16 performance_level_count;

	bool dc_compatible;

	u32 sclk_t;

	struct ci_pl performance_levels[CISLANDS_MAX_HARDWARE_POWERLEVELS];

};



struct ci_dpm_level {

	bool enabled;

	u32 value;

	u32 param1;

};



#define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5

#define MAX_REGULAR_DPM_NUMBER 8

#define CISLAND_MINIMUM_ENGINE_CLOCK 800



struct ci_single_dpm_table {

	u32 count;

	struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];

};



struct ci_dpm_table {

	struct ci_single_dpm_table sclk_table;

	struct ci_single_dpm_table mclk_table;

	struct ci_single_dpm_table pcie_speed_table;

	struct ci_single_dpm_table vddc_table;

	struct ci_single_dpm_table vddci_table;

	struct ci_single_dpm_table mvdd_table;

};



struct ci_mc_reg_entry {

	u32 mclk_max;

	u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

};



struct ci_mc_reg_table {

	u8 last;

	u8 num_entries;

	u16 valid_flag;

	struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];

	SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

};



struct ci_ulv_parm

{

	bool supported;

	u32 cg_ulv_parameter;

	u32 volt_change_delay;

	struct ci_pl pl;

};



#define CISLANDS_MAX_LEAKAGE_COUNT  8



struct ci_leakage_voltage {

	u16 count;

	u16 leakage_id[CISLANDS_MAX_LEAKAGE_COUNT];

	u16 actual_voltage[CISLANDS_MAX_LEAKAGE_COUNT];

};



struct ci_dpm_level_enable_mask {

	u32 uvd_dpm_enable_mask;

	u32 vce_dpm_enable_mask;

	u32 acp_dpm_enable_mask;

	u32 samu_dpm_enable_mask;

	u32 sclk_dpm_enable_mask;

	u32 mclk_dpm_enable_mask;

	u32 pcie_dpm_enable_mask;

};



struct ci_vbios_boot_state

{

	u16 mvdd_bootup_value;

	u16 vddc_bootup_value;

	u16 vddci_bootup_value;

	u32 sclk_bootup_value;

	u32 mclk_bootup_value;

	u16 pcie_gen_bootup_value;

	u16 pcie_lane_bootup_value;

};



struct ci_clock_registers {

	u32 cg_spll_func_cntl;

	u32 cg_spll_func_cntl_2;

	u32 cg_spll_func_cntl_3;

	u32 cg_spll_func_cntl_4;

	u32 cg_spll_spread_spectrum;

	u32 cg_spll_spread_spectrum_2;

	u32 dll_cntl;

	u32 mclk_pwrmgt_cntl;

	u32 mpll_ad_func_cntl;

	u32 mpll_dq_func_cntl;

	u32 mpll_func_cntl;

	u32 mpll_func_cntl_1;

	u32 mpll_func_cntl_2;

	u32 mpll_ss1;

	u32 mpll_ss2;

};



struct ci_thermal_temperature_setting {

	s32 temperature_low;

	s32 temperature_high;

	s32 temperature_shutdown;

};



struct ci_pcie_perf_range {

	u16 max;

	u16 min;

};



enum ci_pt_config_reg_type {

	CISLANDS_CONFIGREG_MMR = 0,

	CISLANDS_CONFIGREG_SMC_IND,

	CISLANDS_CONFIGREG_DIDT_IND,

	CISLANDS_CONFIGREG_CACHE,

	CISLANDS_CONFIGREG_MAX

};



#define POWERCONTAINMENT_FEATURE_BAPM            0x00000001

#define POWERCONTAINMENT_FEATURE_TDCLimit        0x00000002

#define POWERCONTAINMENT_FEATURE_PkgPwrLimit     0x00000004



struct ci_pt_config_reg {

	u32 offset;

	u32 mask;

	u32 shift;

	u32 value;

	enum ci_pt_config_reg_type type;

};



struct ci_pt_defaults {

	u8 svi_load_line_en;

	u8 svi_load_line_vddc;

	u8 tdc_vddc_throttle_release_limit_perc;

	u8 tdc_mawt;

	u8 tdc_waterfall_ctl;

	u8 dte_ambient_temp_base;

	u32 display_cac;

	u32 bapm_temp_gradient;

	u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];

	u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];

};



#define DPMTABLE_OD_UPDATE_SCLK     0x00000001

#define DPMTABLE_OD_UPDATE_MCLK     0x00000002

#define DPMTABLE_UPDATE_SCLK        0x00000004

#define DPMTABLE_UPDATE_MCLK        0x00000008



struct ci_power_info {

	struct ci_dpm_table dpm_table;

	u32 voltage_control;

	u32 mvdd_control;

	u32 vddci_control;

	u32 active_auto_throttle_sources;

	struct ci_clock_registers clock_registers;

	u16 acpi_vddc;

	u16 acpi_vddci;

	enum radeon_pcie_gen force_pcie_gen;

	enum radeon_pcie_gen acpi_pcie_gen;

	struct ci_leakage_voltage vddc_leakage;

	struct ci_leakage_voltage vddci_leakage;

	u16 max_vddc_in_pp_table;

	u16 min_vddc_in_pp_table;

	u16 max_vddci_in_pp_table;

	u16 min_vddci_in_pp_table;

	u32 mclk_strobe_mode_threshold;

	u32 mclk_stutter_mode_threshold;

	u32 mclk_edc_enable_threshold;

	u32 mclk_edc_wr_enable_threshold;

	struct ci_vbios_boot_state vbios_boot_state;

	/* smc offsets */

	u32 sram_end;

	u32 dpm_table_start;

	u32 soft_regs_start;

	u32 mc_reg_table_start;

	u32 fan_table_start;

	u32 arb_table_start;

	/* smc tables */

	SMU7_Discrete_DpmTable smc_state_table;

	SMU7_Discrete_MCRegisters smc_mc_reg_table;

	SMU7_Discrete_PmFuses smc_powertune_table;

	/* other stuff */

	struct ci_mc_reg_table mc_reg_table;

	struct atom_voltage_table vddc_voltage_table;

	struct atom_voltage_table vddci_voltage_table;

	struct atom_voltage_table mvdd_voltage_table;

	struct ci_ulv_parm ulv;

	u32 power_containment_features;

	const struct ci_pt_defaults *powertune_defaults;

	u32 dte_tj_offset;

	bool vddc_phase_shed_control;

	struct ci_thermal_temperature_setting thermal_temp_setting;

	struct ci_dpm_level_enable_mask dpm_level_enable_mask;

	u32 need_update_smu7_dpm_table;

	u32 sclk_dpm_key_disabled;

	u32 mclk_dpm_key_disabled;

	u32 pcie_dpm_key_disabled;

	struct ci_pcie_perf_range pcie_gen_performance;

	struct ci_pcie_perf_range pcie_lane_performance;

	struct ci_pcie_perf_range pcie_gen_powersaving;

	struct ci_pcie_perf_range pcie_lane_powersaving;

	u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS];

	u32 mclk_activity_target;

	u32 low_sclk_interrupt_t;

	u32 last_mclk_dpm_enable_mask;

	u32 sys_pcie_mask;

	/* caps */

	bool caps_power_containment;

	bool caps_cac;

	bool caps_sq_ramping;

	bool caps_db_ramping;

	bool caps_td_ramping;

	bool caps_tcp_ramping;

	bool caps_fps;

	bool caps_sclk_ds;

	bool caps_sclk_ss_support;

	bool caps_mclk_ss_support;

	bool caps_uvd_dpm;

	bool caps_vce_dpm;

	bool caps_samu_dpm;

	bool caps_acp_dpm;

	bool caps_automatic_dc_transition;

	bool caps_sclk_throttle_low_notification;

	bool caps_dynamic_ac_timing;

	/* flags */

	bool thermal_protection;

	bool pcie_performance_request;

	bool dynamic_ss;

	bool dll_default_on;

	bool cac_enabled;

	bool uvd_enabled;

	bool battery_state;

	bool pspp_notify_required;

	bool mem_gddr5;

	bool enable_bapm_feature;

	bool enable_tdc_limit_feature;

	bool enable_pkg_pwr_tracking_feature;

	bool use_pcie_performance_levels;

	bool use_pcie_powersaving_levels;

	/* driver states */

	struct radeon_ps current_rps;

	struct ci_ps current_ps;

	struct radeon_ps requested_rps;

	struct ci_ps requested_ps;

};



#define CISLANDS_VOLTAGE_CONTROL_NONE                   0x0

#define CISLANDS_VOLTAGE_CONTROL_BY_GPIO                0x1

#define CISLANDS_VOLTAGE_CONTROL_BY_SVID2               0x2



#define CISLANDS_Q88_FORMAT_CONVERSION_UNIT             256



#define CISLANDS_VRC_DFLT0                              0x3FFFC000

#define CISLANDS_VRC_DFLT1                              0x000400

#define CISLANDS_VRC_DFLT2                              0xC00080

#define CISLANDS_VRC_DFLT3                              0xC00200

#define CISLANDS_VRC_DFLT4                              0xC01680

#define CISLANDS_VRC_DFLT5                              0xC00033

#define CISLANDS_VRC_DFLT6                              0xC00033

#define CISLANDS_VRC_DFLT7                              0x3FFFC000



#define CISLANDS_CGULVPARAMETER_DFLT                    0x00040035

#define CISLAND_TARGETACTIVITY_DFLT                     30

#define CISLAND_MCLK_TARGETACTIVITY_DFLT                10



#define PCIE_PERF_REQ_REMOVE_REGISTRY   0

#define PCIE_PERF_REQ_FORCE_LOWPOWER    1

#define PCIE_PERF_REQ_PECI_GEN1         2

#define PCIE_PERF_REQ_PECI_GEN2         3

#define PCIE_PERF_REQ_PECI_GEN3         4



int ci_copy_bytes_to_smc(struct radeon_device *rdev,

			 u32 smc_start_address,

			 const u8 *src, u32 byte_count, u32 limit);

void ci_start_smc(struct radeon_device *rdev);

void ci_reset_smc(struct radeon_device *rdev);

int ci_program_jump_on_start(struct radeon_device *rdev);

void ci_stop_smc_clock(struct radeon_device *rdev);

void ci_start_smc_clock(struct radeon_device *rdev);

bool ci_is_smc_running(struct radeon_device *rdev);

PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);

PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev);

int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit);

int ci_read_smc_sram_dword(struct radeon_device *rdev,

			   u32 smc_address, u32 *value, u32 limit);

int ci_write_smc_sram_dword(struct radeon_device *rdev,

			    u32 smc_address, u32 value, u32 limit);



#endif

drivers/gpu/drm/radeon/ci_smc.c

0 → 100644
+262 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2011 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Alex Deucher

 */



#include <linux/firmware.h>

#include "drmP.h"

#include "radeon.h"

#include "cikd.h"

#include "ppsmc.h"

#include "radeon_ucode.h"



static int ci_set_smc_sram_address(struct radeon_device *rdev,

				   u32 smc_address, u32 limit)

{

	if (smc_address & 3)

		return -EINVAL;

	if ((smc_address + 3) > limit)

		return -EINVAL;



	WREG32(SMC_IND_INDEX_0, smc_address);

	WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);



	return 0;

}



int ci_copy_bytes_to_smc(struct radeon_device *rdev,

			 u32 smc_start_address,

			 const u8 *src, u32 byte_count, u32 limit)

{

	u32 data, original_data;

	u32 addr;

	u32 extra_shift;

	int ret;



	if (smc_start_address & 3)

		return -EINVAL;

	if ((smc_start_address + byte_count) > limit)

		return -EINVAL;



	addr = smc_start_address;



	while (byte_count >= 4) {

		/* SMC address space is BE */

		data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];



		ret = ci_set_smc_sram_address(rdev, addr, limit);

		if (ret)

			return ret;



		WREG32(SMC_IND_DATA_0, data);



		src += 4;

		byte_count -= 4;

		addr += 4;

	}



	/* RMW for the final bytes */

	if (byte_count > 0) {

		data = 0;



		ret = ci_set_smc_sram_address(rdev, addr, limit);

		if (ret)

			return ret;



		original_data = RREG32(SMC_IND_DATA_0);



		extra_shift = 8 * (4 - byte_count);



		while (byte_count > 0) {

			data = (data << 8) + *src++;

			byte_count--;

		}



		data <<= extra_shift;



		data |= (original_data & ~((~0UL) << extra_shift));



		ret = ci_set_smc_sram_address(rdev, addr, limit);

		if (ret)

			return ret;



		WREG32(SMC_IND_DATA_0, data);

	}

	return 0;

}



void ci_start_smc(struct radeon_device *rdev)

{

	u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);



	tmp &= ~RST_REG;

	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);

}



void ci_reset_smc(struct radeon_device *rdev)

{

	u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);



	tmp |= RST_REG;

	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);

}



int ci_program_jump_on_start(struct radeon_device *rdev)

{

	static u8 data[] = { 0xE0, 0x00, 0x80, 0x40 };



	return ci_copy_bytes_to_smc(rdev, 0x0, data, 4, sizeof(data)+1);

}



void ci_stop_smc_clock(struct radeon_device *rdev)

{

	u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);



	tmp |= CK_DISABLE;



	WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);

}



void ci_start_smc_clock(struct radeon_device *rdev)

{

	u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);



	tmp &= ~CK_DISABLE;



	WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);

}



bool ci_is_smc_running(struct radeon_device *rdev)

{

	u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

	u32 pc_c = RREG32_SMC(SMC_PC_C);



	if (!(clk & CK_DISABLE) && (0x20100 <= pc_c))

		return true;



	return false;

}



PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg)

{

	u32 tmp;

	int i;



	if (!ci_is_smc_running(rdev))

		return PPSMC_Result_Failed;



	WREG32(SMC_MESSAGE_0, msg);



	for (i = 0; i < rdev->usec_timeout; i++) {

		tmp = RREG32(SMC_RESP_0);

		if (tmp != 0)

			break;

		udelay(1);

	}

	tmp = RREG32(SMC_RESP_0);



	return (PPSMC_Result)tmp;

}



PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev)

{

	u32 tmp;

	int i;



	if (!ci_is_smc_running(rdev))

		return PPSMC_Result_OK;



	for (i = 0; i < rdev->usec_timeout; i++) {

                tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

                if ((tmp & CKEN) == 0)

			break;

                udelay(1);

        }



	return PPSMC_Result_OK;

}



int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit)

{

	u32 ucode_start_address;

	u32 ucode_size;

	const u8 *src;

	u32 data;



	if (!rdev->smc_fw)

		return -EINVAL;



	switch (rdev->family) {

	case CHIP_BONAIRE:

		ucode_start_address = BONAIRE_SMC_UCODE_START;

		ucode_size = BONAIRE_SMC_UCODE_SIZE;

		break;

	default:

		DRM_ERROR("unknown asic in smc ucode loader\n");

		BUG();

	}



	if (ucode_size & 3)

		return -EINVAL;



	src = (const u8 *)rdev->smc_fw->data;

	WREG32(SMC_IND_INDEX_0, ucode_start_address);

	WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);

	while (ucode_size >= 4) {

		/* SMC address space is BE */

		data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];



		WREG32(SMC_IND_DATA_0, data);



		src += 4;

		ucode_size -= 4;

	}

	WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);



	return 0;

}



int ci_read_smc_sram_dword(struct radeon_device *rdev,

			   u32 smc_address, u32 *value, u32 limit)

{

	int ret;



	ret = ci_set_smc_sram_address(rdev, smc_address, limit);

	if (ret)

		return ret;



	*value = RREG32(SMC_IND_DATA_0);

	return 0;

}



int ci_write_smc_sram_dword(struct radeon_device *rdev,

			    u32 smc_address, u32 value, u32 limit)

{

	int ret;



	ret = ci_set_smc_sram_address(rdev, smc_address, limit);

	if (ret)

		return ret;



	WREG32(SMC_IND_DATA_0, value);

	return 0;

}

drivers/gpu/drm/radeon/cik.c

+35 −6
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ MODULE_FIRMWARE("radeon/BONAIRE_mec.bin"); 
MODULE_FIRMWARE("radeon/BONAIRE_mc.bin");

MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin");

MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin");

MODULE_FIRMWARE("radeon/BONAIRE_smc.bin");

MODULE_FIRMWARE("radeon/KAVERI_pfp.bin");

MODULE_FIRMWARE("radeon/KAVERI_me.bin");

MODULE_FIRMWARE("radeon/KAVERI_ce.bin");
@@ -1545,7 +1546,7 @@ static int cik_init_microcode(struct radeon_device *rdev) 
	const char *chip_name;

	size_t pfp_req_size, me_req_size, ce_req_size,

		mec_req_size, rlc_req_size, mc_req_size,

		sdma_req_size;

		sdma_req_size, smc_req_size;

	char fw_name[30];

	int err;
@@ -1561,6 +1562,7 @@ static int cik_init_microcode(struct radeon_device *rdev) 
		rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;

		mc_req_size = CIK_MC_UCODE_SIZE * 4;

		sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;

		smc_req_size = ALIGN(BONAIRE_SMC_UCODE_SIZE, 4);

		break;

	case CHIP_KAVERI:

		chip_name = "KAVERI";
@@ -1652,7 +1654,7 @@ static int cik_init_microcode(struct radeon_device *rdev) 
		err = -EINVAL;

	}



	/* No MC ucode on APUs */

	/* No SMC, MC ucode on APUs */

	if (!(rdev->flags & RADEON_IS_IGP)) {

		snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);

		err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
@@ -1664,6 +1666,21 @@ static int cik_init_microcode(struct radeon_device *rdev) 
			       rdev->mc_fw->size, fw_name);

			err = -EINVAL;

		}



		snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);

		err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);

		if (err) {

			printk(KERN_ERR

			       "smc: error loading firmware \"%s\"\n",

			       fw_name);

			release_firmware(rdev->smc_fw);

			rdev->smc_fw = NULL;

		} else if (rdev->smc_fw->size != smc_req_size) {

			printk(KERN_ERR

			       "cik_smc: Bogus length %zu in firmware \"%s\"\n",

			       rdev->smc_fw->size, fw_name);

			err = -EINVAL;

		}

	}



out:
@@ -1682,6 +1699,8 @@ static int cik_init_microcode(struct radeon_device *rdev) 
		rdev->rlc_fw = NULL;

		release_firmware(rdev->mc_fw);

		rdev->mc_fw = NULL;

		release_firmware(rdev->smc_fw);

		rdev->smc_fw = NULL;

	}

	return err;

}
@@ -6626,8 +6645,12 @@ int cik_irq_set(struct radeon_device *rdev) 
	cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;

	cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;



	if (rdev->flags & RADEON_IS_IGP)

		thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL) &

			~(THERM_INTH_MASK | THERM_INTL_MASK);

	else

		thermal_int = RREG32_SMC(CG_THERMAL_INT) &

			~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);



	/* enable CP interrupts on all rings */

	if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
@@ -6788,7 +6811,10 @@ int cik_irq_set(struct radeon_device *rdev) 


	if (rdev->irq.dpm_thermal) {

		DRM_DEBUG("dpm thermal\n");

		if (rdev->flags & RADEON_IS_IGP)

			thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK;

		else

			thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;

	}



	WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
@@ -6825,7 +6851,10 @@ int cik_irq_set(struct radeon_device *rdev) 
	WREG32(DC_HPD5_INT_CONTROL, hpd5);

	WREG32(DC_HPD6_INT_CONTROL, hpd6);



	if (rdev->flags & RADEON_IS_IGP)

		WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int);

	else

		WREG32_SMC(CG_THERMAL_INT, thermal_int);



	return 0;

}