drm/radeon/kms: add dpm support for KB/KV

	si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \

	r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \

	rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \

	trinity_smc.o ni_dpm.o si_smc.o si_dpm.o

	trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o

radeon-$(CONFIG_COMPAT) += radeon_ioc32.o

radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o

	u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;

	u32 grbm_int_cntl = 0;

	u32 dma_cntl, dma_cntl1;

	u32 thermal_int;

	if (!rdev->irq.installed) {

		WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");

	cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;

	cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;

	thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL) &

		~(THERM_INTH_MASK | THERM_INTL_MASK);

	/* enable CP interrupts on all rings */

	if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {

		DRM_DEBUG("cik_irq_set: sw int gfx\n");

		hpd6 |= DC_HPDx_INT_EN;

	}

	if (rdev->irq.dpm_thermal) {

		DRM_DEBUG("dpm thermal\n");

		thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK;

	}

	WREG32(CP_INT_CNTL_RING0, cp_int_cntl);

	WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);

	WREG32(DC_HPD5_INT_CONTROL, hpd5);

	WREG32(DC_HPD6_INT_CONTROL, hpd6);

	WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int);

	return 0;

}

	bool queue_hotplug = false;

	bool queue_reset = false;

	u32 addr, status, mc_client;

	bool queue_thermal = false;

	if (!rdev->ih.enabled || rdev->shutdown)

		return IRQ_NONE;

				break;

			}

			break;

		case 230: /* thermal low to high */

			DRM_DEBUG("IH: thermal low to high\n");

			rdev->pm.dpm.thermal.high_to_low = false;

			queue_thermal = true;

			break;

		case 231: /* thermal high to low */

			DRM_DEBUG("IH: thermal high to low\n");

			rdev->pm.dpm.thermal.high_to_low = true;

			queue_thermal = true;

			break;

		case 233: /* GUI IDLE */

			DRM_DEBUG("IH: GUI idle\n");

			break;

		case 241: /* SDMA Privileged inst */

		case 247: /* SDMA Privileged inst */

			DRM_ERROR("Illegal instruction in SDMA command stream\n");

				break;

			}

			break;

		case 233: /* GUI IDLE */

			DRM_DEBUG("IH: GUI idle\n");

			break;

		default:

			DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);

			break;

		schedule_work(&rdev->hotplug_work);

	if (queue_reset)

		schedule_work(&rdev->reset_work);

	if (queue_thermal)

		schedule_work(&rdev->pm.dpm.thermal.work);

	rdev->ih.rptr = rptr;

	WREG32(IH_RB_RPTR, rdev->ih.rptr);

	atomic_set(&rdev->ih.lock, 0);

#define CIK_RB_BITMAP_WIDTH_PER_SH  2

/* DIDT IND registers */

#define DIDT_SQ_CTRL0                                     0x0

#       define DIDT_CTRL_EN                               (1 << 0)

#define DIDT_DB_CTRL0                                     0x20

#define DIDT_TD_CTRL0                                     0x40

#define DIDT_TCP_CTRL0                                    0x60

/* SMC IND registers */

#define NB_DPM_CONFIG_1                                   0x3F9E8

#       define Dpm0PgNbPsLo(x)                            ((x) << 0)

#       define Dpm0PgNbPsLo_MASK                          0x000000ff

#       define Dpm0PgNbPsLo_SHIFT                         0

#       define Dpm0PgNbPsHi(x)                            ((x) << 8)

#       define Dpm0PgNbPsHi_MASK                          0x0000ff00

#       define Dpm0PgNbPsHi_SHIFT                         8

#       define DpmXNbPsLo(x)                              ((x) << 16)

#       define DpmXNbPsLo_MASK                            0x00ff0000

#       define DpmXNbPsLo_SHIFT                           16

#       define DpmXNbPsHi(x)                              ((x) << 24)

#       define DpmXNbPsHi_MASK                            0xff000000

#       define DpmXNbPsHi_SHIFT                           24

#define SMC_SYSCON_MSG_ARG_0                              0x80000068

#define GENERAL_PWRMGT                                    0xC0200000

#       define GLOBAL_PWRMGT_EN                           (1 << 0)

#       define GPU_COUNTER_CLK                            (1 << 15)

#define SCLK_PWRMGT_CNTL                                  0xC0200008

#       define RESET_BUSY_CNT                             (1 << 4)

#       define RESET_SCLK_CNT                             (1 << 5)

#       define DYNAMIC_PM_EN                              (1 << 21)

#define CG_FTV_0                                          0xC02001A8

#define LCAC_SX0_OVR_SEL                                  0xC0400D04

#define LCAC_SX0_OVR_VAL                                  0xC0400D08

#define LCAC_MC0_OVR_SEL                                  0xC0400D34

#define LCAC_MC0_OVR_VAL                                  0xC0400D38

#define LCAC_MC1_OVR_SEL                                  0xC0400D40

#define LCAC_MC1_OVR_VAL                                  0xC0400D44

#define LCAC_MC2_OVR_SEL                                  0xC0400D4C

#define LCAC_MC2_OVR_VAL                                  0xC0400D50

#define LCAC_MC3_OVR_SEL                                  0xC0400D58

#define LCAC_MC3_OVR_VAL                                  0xC0400D5C

#define LCAC_CPL_OVR_SEL                                  0xC0400D84

#define LCAC_CPL_OVR_VAL                                  0xC0400D88

#define	CG_MULT_THERMAL_STATUS				0xC0300014

#define		ASIC_MAX_TEMP(x)			((x) << 0)

#define		ASIC_MAX_TEMP_MASK			0x000001ff

#	define ZCLK_SEL(x)				((x) << 8)

#	define ZCLK_SEL_MASK				0xFF00

#define	CG_THERMAL_INT_CTRL				0xC2100028

#define		DIG_THERM_INTH(x)			((x) << 0)

#define		DIG_THERM_INTH_MASK			0x000000FF

#define		DIG_THERM_INTH_SHIFT			0

#define		DIG_THERM_INTL(x)			((x) << 8)

#define		DIG_THERM_INTL_MASK			0x0000FF00

#define		DIG_THERM_INTL_SHIFT			8

#define 	THERM_INTH_MASK				(1 << 24)

#define 	THERM_INTL_MASK				(1 << 25)

/* PCIE registers idx/data 0x38/0x3c */

#define PB0_PIF_PWRDOWN_0                                 0x1100012 /* PCIE */

#       define PLL_POWER_STATE_IN_TXS2_0(x)               ((x) << 7)

#define PCIE_INDEX  					0x38

#define PCIE_DATA  					0x3C

#define SMC_IND_INDEX_0  				0x200

#define SMC_IND_DATA_0  				0x204

#define SMC_IND_ACCESS_CNTL  				0x240

#define		AUTO_INCREMENT_IND_0			(1 << 0)

#define SMC_MESSAGE_0  					0x250

#define		SMC_MSG_MASK				0xffff

#define SMC_RESP_0  					0x254

#define		SMC_RESP_MASK				0xffff

#define SMC_MSG_ARG_0  					0x290

#define VGA_HDP_CONTROL  				0x328

#define		VGA_MEMORY_DISABLE				(1 << 4)

/*

 * Copyright 2013 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef __KV_DPM_H__

#define __KV_DPM_H__

#define SMU__NUM_SCLK_DPM_STATE  8

#define SMU__NUM_MCLK_DPM_LEVELS 4

#define SMU__NUM_LCLK_DPM_LEVELS 8

#define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */

#include "smu7_fusion.h"

#include "trinity_dpm.h"

#include "ppsmc.h"

#define KV_NUM_NBPSTATES   4

enum kv_pt_config_reg_type {

	KV_CONFIGREG_MMR = 0,

	KV_CONFIGREG_SMC_IND,

	KV_CONFIGREG_DIDT_IND,

	KV_CONFIGREG_CACHE,

	KV_CONFIGREG_MAX

};

struct kv_pt_config_reg {

	u32 offset;

	u32 mask;

	u32 shift;

	u32 value;

	enum kv_pt_config_reg_type type;

};

struct kv_lcac_config_values {

	u32 block_id;

	u32 signal_id;

	u32 t;

};

struct kv_lcac_config_reg {

	u32 cntl;

	u32 block_mask;

	u32 block_shift;

	u32 signal_mask;

	u32 signal_shift;

	u32 t_mask;

	u32 t_shift;

	u32 enable_mask;

	u32 enable_shift;

};

struct kv_pl {

	u32 sclk;

	u8 vddc_index;

	u8 ds_divider_index;

	u8 ss_divider_index;

	u8 allow_gnb_slow;

	u8 force_nbp_state;

	u8 display_wm;

	u8 vce_wm;

};

struct kv_ps {

	struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];

	u32 num_levels;

	bool need_dfs_bypass;

	u8 dpm0_pg_nb_ps_lo;

	u8 dpm0_pg_nb_ps_hi;

	u8 dpmx_nb_ps_lo;

	u8 dpmx_nb_ps_hi;

};

struct kv_sys_info {

	u32 bootup_uma_clk;

	u32 bootup_sclk;

	u32 dentist_vco_freq;

	u32 nb_dpm_enable;

	u32 nbp_memory_clock[KV_NUM_NBPSTATES];

	u32 nbp_n_clock[KV_NUM_NBPSTATES];

	u16 bootup_nb_voltage_index;

	u8 htc_tmp_lmt;

	u8 htc_hyst_lmt;

	struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;

	struct sumo_vid_mapping_table vid_mapping_table;

	u32 uma_channel_number;

};

struct kv_power_info {

	u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];

	u32 voltage_drop_t;

	struct kv_sys_info sys_info;

	struct kv_pl boot_pl;

	bool enable_nb_ps_policy;

	bool disable_nb_ps3_in_battery;

	bool video_start;

	bool battery_state;

	u32 lowest_valid;

	u32 highest_valid;

	u16 high_voltage_t;

	bool cac_enabled;

	bool bapm_enable;

	/* smc offsets */

	u32 sram_end;

	u32 dpm_table_start;

	u32 soft_regs_start;

	/* dpm SMU tables */

	u8 graphics_dpm_level_count;

	u8 uvd_level_count;

	u8 vce_level_count;

	u8 acp_level_count;

	u8 samu_level_count;

	u16 fps_high_t;

	SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];

	SMU7_Fusion_ACPILevel acpi_level;

	SMU7_Fusion_UvdLevel uvd_level[SMU7_MAX_LEVELS_UVD];

	SMU7_Fusion_ExtClkLevel vce_level[SMU7_MAX_LEVELS_VCE];

	SMU7_Fusion_ExtClkLevel acp_level[SMU7_MAX_LEVELS_ACP];

	SMU7_Fusion_ExtClkLevel samu_level[SMU7_MAX_LEVELS_SAMU];

	u8 uvd_boot_level;

	u8 vce_boot_level;

	u8 acp_boot_level;

	u8 samu_boot_level;

	u8 uvd_interval;

	u8 vce_interval;

	u8 acp_interval;

	u8 samu_interval;

	u8 graphics_boot_level;

	u8 graphics_interval;

	u8 graphics_therm_throttle_enable;

	u8 graphics_voltage_change_enable;

	u8 graphics_clk_slow_enable;

	u8 graphics_clk_slow_divider;

	u8 fps_low_t;

	u32 low_sclk_interrupt_t;

	bool uvd_power_gated;

	bool vce_power_gated;

	bool acp_power_gated;

	bool samu_power_gated;

	bool nb_dpm_enabled;

	/* flags */

	bool enable_didt;

	bool enable_dpm;

	bool enable_auto_thermal_throttling;

	bool enable_nb_dpm;

	/* caps */

	bool caps_cac;

	bool caps_power_containment;

	bool caps_sq_ramping;

	bool caps_db_ramping;

	bool caps_td_ramping;

	bool caps_tcp_ramping;

	bool caps_sclk_throttle_low_notification;

	bool caps_fps;

	bool caps_uvd_dpm;

	bool caps_uvd_pg;

	bool caps_vce_pg;

	bool caps_samu_pg;

	bool caps_acp_pg;

	bool caps_stable_p_state;

	bool caps_enable_dfs_bypass;

	bool caps_sclk_ds;

	struct radeon_ps current_rps;

	struct kv_ps current_ps;

	struct radeon_ps requested_rps;

	struct kv_ps requested_ps;

};

/* kv_smc.c */

int kv_notify_message_to_smu(struct radeon_device *rdev, u32 id);

int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask);

int kv_send_msg_to_smc_with_parameter(struct radeon_device *rdev,

				      PPSMC_Msg msg, u32 parameter);

int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,

			   u32 *value, u32 limit);

int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable);

int kv_copy_bytes_to_smc(struct radeon_device *rdev,

			 u32 smc_start_address,

			 const u8 *src, u32 byte_count, u32 limit);

#endif