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Commit c8ebc2b0 authored by Daniel Vetter's avatar Daniel Vetter Committed by Keith Packard
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drm/915: fix relaxed tiling on gen2: tile height 



A tile on gen2 has a size of 2kb, stride of 128 bytes and 16 rows.

Userspace was broken and assumed 8 rows. Chris Wilson noted that the
kernel unfortunately can't reliable check that because libdrm rounds
up the size to the next bucket.

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
parent d3bcb757

drivers/gpu/drm/i915/i915_gem.c

+3 −2
Original line number Diff line number Diff line
@@ -1449,8 +1449,9 @@ i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj) 
	 * edge of an even tile row (where tile rows are counted as if the bo is

	 * placed in a fenced gtt region).

	 */

	if (IS_GEN2(dev) ||

	    (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))

	if (IS_GEN2(dev))

		tile_height = 16;

	else if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))

		tile_height = 32;

	else

		tile_height = 8;