Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Skip to content
Commit c8dd5110 authored by Boojin Kim's avatar Boojin Kim Committed by Kukjin Kim
Browse files

ARM: EXYNOS: Remove the L2 cache latency setting for EXYNOS5



Since SYSRAM set the L2 cache latency on EXYNOS5 SoCs,
no longer need that in the kernel. It helps to reduce
booting time (no need cache disable and cache enable).

Signed-off-by: default avatarBoojin Kim <boojin.kim@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 65ab16fd
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment