Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c4051935 authored by Xing Zheng's avatar Xing Zheng Committed by Heiko Stuebner
Browse files

clk: rockchip: rk3036: fix the div offset for emac clock 



Due to reference to old version TRM, there are incorrect emac clock node.
The SEL_21_9 is used for the parent div, the SEL_21_4 is used for the
child div.

Signed-off-by: default avatarXing Zheng <zhengxing@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent b29de2de

drivers/clk/rockchip/clk-rk3036.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -344,12 +344,12 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { 
			RK2928_CLKGATE_CON(10), 5, GFLAGS),

			RK2928_CLKGATE_CON(10), 5, GFLAGS),





	COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,

	COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,

			RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),

			RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),

	MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,

	MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,

			RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),

			RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),





	COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,

	COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,

			RK2928_CLKSEL_CON(21), 9, 5, DFLAGS,

			RK2928_CLKSEL_CON(21), 4, 5, DFLAGS,

			RK2928_CLKGATE_CON(2), 6, GFLAGS),

			RK2928_CLKGATE_CON(2), 6, GFLAGS),





	MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,

	MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,