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Commit b29de2de authored by Xing Zheng's avatar Xing Zheng Committed by Heiko Stuebner
Browse files

clk: rockchip: rk3036: fix uarts clock error 



Due to a copy-paste error the uart1 and uart2 clock div set
incorrect, fix it.

Signed-off-by: default avatarXing Zheng <zhengxing@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 99222c9e

drivers/clk/rockchip/clk-rk3036.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -242,11 +242,11 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { 
			RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,

			RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,

			RK2928_CLKGATE_CON(1), 8, GFLAGS),

			RK2928_CLKGATE_CON(1), 8, GFLAGS),

	COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0,

	COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0,

			RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,

			RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,

			RK2928_CLKGATE_CON(1), 8, GFLAGS),

			RK2928_CLKGATE_CON(1), 10, GFLAGS),

	COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0,

	COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0,

			RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,

			RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,

			RK2928_CLKGATE_CON(1), 8, GFLAGS),

			RK2928_CLKGATE_CON(1), 12, GFLAGS),

	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,

	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,

			RK2928_CLKSEL_CON(17), 0,

			RK2928_CLKSEL_CON(17), 0,

			RK2928_CLKGATE_CON(1), 9, GFLAGS,

			RK2928_CLKGATE_CON(1), 9, GFLAGS,