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Commit c2599da7 authored by Thierry Reding's avatar Thierry Reding
Browse files

arm64: tegra: Add display nodes on Tegra186 



Adds the device tree nodes for the display hub and display controllers
as well as the DPAUX, DSI and SOR controllers.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent b30a8e61

arch/arm64/boot/dts/nvidia/tegra186.dtsi

+258 −0
Original line number Diff line number Diff line
@@ -546,6 +546,129 @@ 
		#size-cells = <1>;



		ranges = <0x15000000 0x0 0x15000000 0x01000000>;

		iommus = <&smmu TEGRA186_SID_HOST1X>;



		dpaux1: dpaux@15040000 {

			compatible = "nvidia,tegra186-dpaux";

			reg = <0x15040000 0x10000>;

			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA186_CLK_DPAUX1>,

				 <&bpmp TEGRA186_CLK_PLLDP>;

			clock-names = "dpaux", "parent";

			resets = <&bpmp TEGRA186_RESET_DPAUX1>;

			reset-names = "dpaux";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;



			state_dpaux1_aux: pinmux-aux {

				groups = "dpaux-io";

				function = "aux";

			};



			state_dpaux1_i2c: pinmux-i2c {

				groups = "dpaux-io";

				function = "i2c";

			};



			state_dpaux1_off: pinmux-off {

				groups = "dpaux-io";

				function = "off";

			};



			i2c-bus {

				#address-cells = <1>;

				#size-cells = <0>;

			};

		};



		display-hub@15200000 {

			compatible = "nvidia,tegra186-display", "simple-bus";

			resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,

				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,

				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,

				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,

				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,

				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,

				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;

			reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",

				      "wgrp3", "wgrp4", "wgrp5";

			clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,

				 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,

				 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;

			clock-names = "disp", "dsc", "hub";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;



			#address-cells = <1>;

			#size-cells = <1>;



			ranges = <0x15200000 0x15200000 0x40000>;



			display@15200000 {

				compatible = "nvidia,tegra186-dc";

				reg = <0x15200000 0x10000>;

				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;

				clock-names = "dc";

				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;

				reset-names = "dc";



				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;



				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;

				nvidia,head = <0>;

			};



			display@15210000 {

				compatible = "nvidia,tegra186-dc";

				reg = <0x15210000 0x10000>;

				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;

				clock-names = "dc";

				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;

				reset-names = "dc";



				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;

				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;



				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;

				nvidia,head = <1>;

			};



			display@15220000 {

				compatible = "nvidia,tegra186-dc";

				reg = <0x15220000 0x10000>;

				interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;

				clock-names = "dc";

				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;

				reset-names = "dc";



				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;

				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;



				nvidia,outputs = <&sor0 &sor1>;

				nvidia,head = <2>;

			};

		};



		dsia: dsi@15300000 {

			compatible = "nvidia,tegra186-dsi";

			reg = <0x15300000 0x10000>;

			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA186_CLK_DSI>,

				 <&bpmp TEGRA186_CLK_DSIA_LP>,

				 <&bpmp TEGRA186_CLK_PLLD>;

			clock-names = "dsi", "lp", "parent";

			resets = <&bpmp TEGRA186_RESET_DSI>;

			reset-names = "dsi";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

		};



		vic@15340000 {

			compatible = "nvidia,tegra186-vic";
@@ -558,6 +681,141 @@ 


			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;

		};



		dsib: dsi@15400000 {

			compatible = "nvidia,tegra186-dsi";

			reg = <0x15400000 0x10000>;

			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA186_CLK_DSIB>,

				 <&bpmp TEGRA186_CLK_DSIB_LP>,

				 <&bpmp TEGRA186_CLK_PLLD>;

			clock-names = "dsi", "lp", "parent";

			resets = <&bpmp TEGRA186_RESET_DSIB>;

			reset-names = "dsi";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

		};



		sor0: sor@15540000 {

			compatible = "nvidia,tegra186-sor";

			reg = <0x15540000 0x10000>;

			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA186_CLK_SOR0>,

				 <&bpmp TEGRA186_CLK_SOR0_OUT>,

				 <&bpmp TEGRA186_CLK_PLLD2>,

				 <&bpmp TEGRA186_CLK_PLLDP>,

				 <&bpmp TEGRA186_CLK_SOR_SAFE>,

				 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;

			clock-names = "sor", "out", "parent", "dp", "safe",

				      "pad";

			resets = <&bpmp TEGRA186_RESET_SOR0>;

			reset-names = "sor";

			pinctrl-0 = <&state_dpaux_aux>;

			pinctrl-1 = <&state_dpaux_i2c>;

			pinctrl-2 = <&state_dpaux_off>;

			pinctrl-names = "aux", "i2c", "off";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

			nvidia,interface = <0>;

		};



		sor1: sor@15580000 {

			compatible = "nvidia,tegra186-sor1";

			reg = <0x15580000 0x10000>;

			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA186_CLK_SOR1>,

				 <&bpmp TEGRA186_CLK_SOR1_OUT>,

				 <&bpmp TEGRA186_CLK_PLLD3>,

				 <&bpmp TEGRA186_CLK_PLLDP>,

				 <&bpmp TEGRA186_CLK_SOR_SAFE>,

				 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;

			clock-names = "sor", "out", "parent", "dp", "safe",

				      "pad";

			resets = <&bpmp TEGRA186_RESET_SOR1>;

			reset-names = "sor";

			pinctrl-0 = <&state_dpaux1_aux>;

			pinctrl-1 = <&state_dpaux1_i2c>;

			pinctrl-2 = <&state_dpaux1_off>;

			pinctrl-names = "aux", "i2c", "off";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

			nvidia,interface = <1>;

		};



		dpaux: dpaux@155c0000 {

			compatible = "nvidia,tegra186-dpaux";

			reg = <0x155c0000 0x10000>;

			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA186_CLK_DPAUX>,

				 <&bpmp TEGRA186_CLK_PLLDP>;

			clock-names = "dpaux", "parent";

			resets = <&bpmp TEGRA186_RESET_DPAUX>;

			reset-names = "dpaux";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;



			state_dpaux_aux: pinmux-aux {

				groups = "dpaux-io";

				function = "aux";

			};



			state_dpaux_i2c: pinmux-i2c {

				groups = "dpaux-io";

				function = "i2c";

			};



			state_dpaux_off: pinmux-off {

				groups = "dpaux-io";

				function = "off";

			};



			i2c-bus {

				#address-cells = <1>;

				#size-cells = <0>;

			};

		};



		padctl@15880000 {

			compatible = "nvidia,tegra186-dsi-padctl";

			reg = <0x15880000 0x10000>;

			resets = <&bpmp TEGRA186_RESET_DSI>;

			reset-names = "dsi";

			status = "disabled";

		};



		dsic: dsi@15900000 {

			compatible = "nvidia,tegra186-dsi";

			reg = <0x15900000 0x10000>;

			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA186_CLK_DSIC>,

				 <&bpmp TEGRA186_CLK_DSIC_LP>,

				 <&bpmp TEGRA186_CLK_PLLD>;

			clock-names = "dsi", "lp", "parent";

			resets = <&bpmp TEGRA186_RESET_DSIC>;

			reset-names = "dsi";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

		};



		dsid: dsi@15940000 {

			compatible = "nvidia,tegra186-dsi";

			reg = <0x15940000 0x10000>;

			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA186_CLK_DSID>,

				 <&bpmp TEGRA186_CLK_DSID_LP>,

				 <&bpmp TEGRA186_CLK_PLLD>;

			clock-names = "dsi", "lp", "parent";

			resets = <&bpmp TEGRA186_RESET_DSID>;

			reset-names = "dsi";

			status = "disabled";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

		};

	};



	gpu@17000000 {