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Commit b30a8e61 authored by Thierry Reding's avatar Thierry Reding
Browse files

arm64: tegra: Add SMMU node for Tegra186 



Add the DT node for ARM SMMU on Tegra186.

Signed-off-by: default avatarKrishna Reddy <vdumpa@nvidia.com>
Reviewed-by: default avatarMikko Perttunen <mperttunen@nvidia.com>
Tested-by: default avatarMikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 301f12dc

arch/arm64/boot/dts/nvidia/tegra186.dtsi

+73 −0
Original line number Diff line number Diff line
@@ -457,6 +457,79 @@ 
		};

	};



	smmu: iommu@12000000 {

		compatible = "arm,mmu-500";

		reg = <0 0x12000000 0 0x800000>;

		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;

		stream-match-mask = <0x7f80>;

		#global-interrupts = <1>;

		#iommu-cells = <1>;

	};



	host1x@13e00000 {

		compatible = "nvidia,tegra186-host1x", "simple-bus";

		reg = <0x0 0x13e00000 0x0 0x10000>,