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Commit c14deee3 authored by Michael Turquette's avatar Michael Turquette
Browse files

Merge tag 'clk/for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next 

clk/tegra: Changes for v4.1-rc1

These are mostly cleanups that I've been carrying in my local tree for
far too long. In addition to those, there are some preparatory patches
for the upcoming Tegra210 support and a patch to enable clocks needed
for HDMI audio support.
parents 820ad975 c1d676ce

drivers/clk/tegra/clk-pll.c

+4 −3
Original line number Diff line number Diff line
@@ -981,7 +981,7 @@ static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate, 
	struct tegra_clk_pll *pll = to_clk_pll(hw);

	struct tegra_clk_pll_freq_table cfg, old_cfg;

	unsigned long flags = 0;

	int ret = 0;

	int ret;



	ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);

	if (ret < 0)
@@ -1005,7 +1005,7 @@ static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate, 
				unsigned long *prate)

{

	struct tegra_clk_pll_freq_table cfg;

	int ret = 0, p_div;

	int ret, p_div;

	u64 output_rate = *prate;



	ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
@@ -1073,7 +1073,7 @@ static int clk_pllc_enable(struct clk_hw *hw) 
{

	struct tegra_clk_pll *pll = to_clk_pll(hw);

	u32 val;

	int ret = 0;

	int ret;

	unsigned long flags = 0;



	if (pll->lock)
@@ -1223,6 +1223,7 @@ static long _pllre_calc_rate(struct tegra_clk_pll *pll, 


	return output_rate;

}



static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,

				unsigned long parent_rate)

{

drivers/clk/tegra/clk-tegra-fixed.c

+13 −11
Original line number Diff line number Diff line
@@ -30,13 +30,12 @@ 
#define OSC_CTRL_OSC_FREQ_SHIFT		28

#define OSC_CTRL_PLL_REF_DIV_SHIFT	26



int __init tegra_osc_clk_init(void __iomem *clk_base,

				struct tegra_clk *tegra_clks,

				unsigned long *input_freqs, int num,

				unsigned long *osc_freq,

int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,

			      unsigned long *input_freqs, unsigned int num,

			      unsigned int clk_m_div, unsigned long *osc_freq,

			      unsigned long *pll_ref_freq)

{

	struct clk *clk;

	struct clk *clk, *osc;

	struct clk **dt_clk;

	u32 val, pll_ref_div;

	unsigned osc_idx;
@@ -54,22 +53,25 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, 
		return -EINVAL;

	}



	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, tegra_clks);

	osc = clk_register_fixed_rate(NULL, "osc", NULL, CLK_IS_ROOT,

				      *osc_freq);



	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);

	if (!dt_clk)

		return 0;



	clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,

				      *osc_freq);

	clk = clk_register_fixed_factor(NULL, "clk_m", "osc",

					0, 1, clk_m_div);

	*dt_clk = clk;



	/* pll_ref */

	val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;

	pll_ref_div = 1 << val;

	dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, tegra_clks);

	dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, clks);

	if (!dt_clk)

		return 0;



	clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",

	clk = clk_register_fixed_factor(NULL, "pll_ref", "osc",

					0, 1, pll_ref_div);

	*dt_clk = clk;

drivers/clk/tegra/clk-tegra-periph.c

+1 −1
Original line number Diff line number Diff line
@@ -218,7 +218,7 @@ 
		.clk_id = _clk_id,					\

		.p.parent_name = _parent_name,				\

		.periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0,		\

				_clk_num, _gate_flags, 0, NULL),	\

				_clk_num, _gate_flags, NULL, NULL),	\

		.flags = _flags						\

	}

drivers/clk/tegra/clk-tegra114.c

+4 −32
Original line number Diff line number Diff line
@@ -940,36 +940,6 @@ static struct clk **clks; 
static unsigned long osc_freq;

static unsigned long pll_ref_freq;



static int __init tegra114_osc_clk_init(void __iomem *clk_base)

{

	struct clk *clk;

	u32 val, pll_ref_div;



	val = readl_relaxed(clk_base + OSC_CTRL);



	osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT];

	if (!osc_freq) {

		WARN_ON(1);

		return -EINVAL;

	}



	/* clk_m */

	clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,

				      osc_freq);

	clks[TEGRA114_CLK_CLK_M] = clk;



	/* pll_ref */

	val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;

	pll_ref_div = 1 << val;

	clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",

					CLK_SET_RATE_PARENT, 1, pll_ref_div);

	clks[TEGRA114_CLK_PLL_REF] = clk;



	pll_ref_freq = osc_freq / pll_ref_div;



	return 0;

}



static void __init tegra114_fixed_clk_init(void __iomem *clk_base)

{

	struct clk *clk;
@@ -1263,6 +1233,7 @@ static void tegra114_wait_cpu_in_reset(u32 cpu) 
		cpu_relax();

	} while (!(reg & (1 << cpu)));  /* check CPU been reset or not */

}



static void tegra114_disable_cpu_clock(u32 cpu)

{

	/* flow controller would take care in the power sequence. */
@@ -1351,7 +1322,6 @@ static void __init tegra114_clock_apply_init_table(void) 
	tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);

}





/**

 * tegra114_car_barrier - wait for pending writes to the CAR to complete

 *
@@ -1505,7 +1475,9 @@ static void __init tegra114_clock_init(struct device_node *np) 
	if (!clks)

		return;



	if (tegra114_osc_clk_init(clk_base) < 0)

	if (tegra_osc_clk_init(clk_base, tegra114_clks, tegra114_input_freq,

			       ARRAY_SIZE(tegra114_input_freq), 1, &osc_freq,

			       &pll_ref_freq) < 0)

		return;



	tegra114_fixed_clk_init(clk_base);

drivers/clk/tegra/clk-tegra124.c

+15 −7
Original line number Diff line number Diff line
@@ -1014,6 +1014,9 @@ static struct tegra_devclk devclks[] __initdata = { 
	{ .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE },

	{ .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },

	{ .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER },

	{ .con_id = "hda", .dt_id = TEGRA124_CLK_HDA },

	{ .con_id = "hda2codec_2x", .dt_id = TEGRA124_CLK_HDA2CODEC_2X },

	{ .con_id = "hda2hdmi", .dt_id = TEGRA124_CLK_HDA2HDMI },

};



static struct clk **clks;
@@ -1110,16 +1113,18 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base, 
					1, 2);

	clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;



	clk = clk_register_gate(NULL, "plld_dsi", "plld_out0", 0,

	clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,

				clk_base + PLLD_MISC, 30, 0, &pll_d_lock);

	clks[TEGRA124_CLK_PLLD_DSI] = clk;

	clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk;



	clk = tegra_clk_register_periph_gate("dsia", "plld_dsi", 0, clk_base,

					     0, 48, periph_clk_enb_refcnt);

	clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,

					     clk_base, 0, 48,

					     periph_clk_enb_refcnt);

	clks[TEGRA124_CLK_DSIA] = clk;



	clk = tegra_clk_register_periph_gate("dsib", "plld_dsi", 0, clk_base,

					     0, 82, periph_clk_enb_refcnt);

	clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,

					     clk_base, 0, 82,

					     periph_clk_enb_refcnt);

	clks[TEGRA124_CLK_DSIB] = clk;



	/* emc mux */
@@ -1395,6 +1400,8 @@ static struct tegra_clk_init_table common_init_table[] __initdata = { 
static struct tegra_clk_init_table tegra124_init_table[] __initdata = {

	{TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0},

	{TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},

	{TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0},

	{TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0},

	/* This MUST be the last entry. */

	{TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},

};
@@ -1475,7 +1482,8 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np) 
		return;



	if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,

		ARRAY_SIZE(tegra124_input_freq), &osc_freq, &pll_ref_freq) < 0)

			       ARRAY_SIZE(tegra124_input_freq), 1, &osc_freq,

			       &pll_ref_freq) < 0)

		return;



	tegra_fixed_clk_init(tegra124_clks);