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Commit c1d676ce authored by Thierry Reding's avatar Thierry Reding
Browse files

clk: tegra: Use the proper parent for plld_dsi 



The current parent, plld_out0, does not exist. The proper name is
pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to
be more consistent with other clock names.

Fixes: b270491e ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux")
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent a84724a1

drivers/clk/tegra/clk-tegra124.c

+8 −6
Original line number Diff line number Diff line
@@ -1113,16 +1113,18 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base, 
					1, 2);

	clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;



	clk = clk_register_gate(NULL, "plld_dsi", "plld_out0", 0,

	clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,

				clk_base + PLLD_MISC, 30, 0, &pll_d_lock);

	clks[TEGRA124_CLK_PLLD_DSI] = clk;

	clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk;



	clk = tegra_clk_register_periph_gate("dsia", "plld_dsi", 0, clk_base,

					     0, 48, periph_clk_enb_refcnt);

	clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,

					     clk_base, 0, 48,

					     periph_clk_enb_refcnt);

	clks[TEGRA124_CLK_DSIA] = clk;



	clk = tegra_clk_register_periph_gate("dsib", "plld_dsi", 0, clk_base,

					     0, 82, periph_clk_enb_refcnt);

	clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,

					     clk_base, 0, 82,

					     periph_clk_enb_refcnt);

	clks[TEGRA124_CLK_DSIB] = clk;



	/* emc mux */

include/dt-bindings/clock/tegra124-car-common.h

+1 −1
Original line number Diff line number Diff line
@@ -297,7 +297,7 @@ 
#define TEGRA124_CLK_PLL_C4 270

#define TEGRA124_CLK_PLL_DP 271

#define TEGRA124_CLK_PLL_E_MUX 272

#define TEGRA124_CLK_PLLD_DSI 273

#define TEGRA124_CLK_PLL_D_DSI_OUT 273

/* 274 */

/* 275 */

/* 276 */