Commit c08ceea3 authored Sep 25, 2013 by Andrew Bresticker Committed by Tomasz Figa Jan 08, 2014

ARM: dts: exynos5250: add input clocks to audss clock controller



Specify pll_ref, pll_in, sclk_audio, and sclk_pcm_in for the AudioSS
clock controller.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>

parent 35399dda

arch/arm/boot/dts/exynos5250.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -88,6 +88,8 @@
		compatible = "samsung,exynos5250-audss-clock";
		reg = <0x03810000 0x0C>;
		#clock-cells = <1>;
		clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>;
		clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
		};

		timer {