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Commit c03c45ef authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
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Merge 4.19.105 into android-4.19 



Changes in 4.19.105
	Input: synaptics - switch T470s to RMI4 by default
	Input: synaptics - enable SMBus on ThinkPad L470
	Input: synaptics - remove the LEN0049 dmi id from topbuttonpad list
	ALSA: usb-audio: Fix UAC2/3 effect unit parsing
	ALSA: hda/realtek - Fix silent output on MSI-GL73
	ALSA: usb-audio: Apply sample rate quirk for Audioengine D1
	arm64: cpufeature: Set the FP/SIMD compat HWCAP bits properly
	arm64: nofpsmid: Handle TIF_FOREIGN_FPSTATE flag cleanly
	ALSA: usb-audio: sound: usb: usb true/false for bool return type
	ALSA: usb-audio: Add clock validity quirk for Denon MC7000/MCX8000
	ext4: don't assume that mmp_nodename/bdevname have NUL
	ext4: fix support for inode sizes > 1024 bytes
	ext4: fix checksum errors with indexed dirs
	ext4: add cond_resched() to ext4_protect_reserved_inode
	ext4: improve explanation of a mount failure caused by a misconfigured kernel
	Btrfs: fix race between using extent maps and merging them
	btrfs: ref-verify: fix memory leaks
	btrfs: print message when tree-log replay starts
	btrfs: log message when rw remount is attempted with unclean tree-log
	ARM: npcm: Bring back GPIOLIB support
	arm64: ssbs: Fix context-switch when SSBS is present on all CPUs
	KVM: nVMX: Use correct root level for nested EPT shadow page tables
	perf/x86/amd: Add missing L2 misses event spec to AMD Family 17h's event map
	nvme: fix the parameter order for nvme_get_log in nvme_get_fw_slot_info
	IB/hfi1: Acquire lock to release TID entries when user file is closed
	IB/hfi1: Close window for pq and request coliding
	IB/rdmavt: Reset all QPs when the device is shut down
	RDMA/core: Fix invalid memory access in spec_filter_size
	RDMA/hfi1: Fix memory leak in _dev_comp_vect_mappings_create
	RDMA/rxe: Fix soft lockup problem due to using tasklets in softirq
	RDMA/core: Fix protection fault in get_pkey_idx_qp_list
	s390/time: Fix clk type in get_tod_clock
	perf/x86/intel: Fix inaccurate period in context switch for auto-reload
	hwmon: (pmbus/ltc2978) Fix PMBus polling of MFR_COMMON definitions.
	NFSv4.1 make cachethis=no for writes
	jbd2: move the clearing of b_modified flag to the journal_unmap_buffer()
	jbd2: do not clear the BH_Mapped flag when forgetting a metadata buffer
	KVM: x86/mmu: Fix struct guest_walker arrays for 5-level paging
	Linux 4.19.105

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
Change-Id: I411bf0e21a24cee878f1a114175090e8fe69be46
parents 50297eab 4fccc250

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 4

PATCHLEVEL = 19

SUBLEVEL = 104

SUBLEVEL = 105

EXTRAVERSION =

NAME = "People's Front"

arch/arm/mach-npcm/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ config ARCH_NPCM7XX 
	depends on ARCH_MULTI_V7

	select PINCTRL_NPCM7XX

	select NPCM7XX_TIMER

	select ARCH_REQUIRE_GPIOLIB

	select GPIOLIB

	select CACHE_L2X0

	select ARM_GIC

	select HAVE_ARM_TWD if SMP

arch/arm64/kernel/cpufeature.c

+45 −7
Original line number Diff line number Diff line
@@ -42,9 +42,7 @@ EXPORT_SYMBOL_GPL(elf_hwcap); 
#define COMPAT_ELF_HWCAP_DEFAULT	\

				(COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\

				 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\

				 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\

				 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\

				 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\

				 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\

				 COMPAT_HWCAP_LPAE)

unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;

unsigned int compat_elf_hwcap2 __read_mostly;
@@ -1341,17 +1339,30 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
	{},

};



#define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)	\

	{							\

		.desc = #cap,					\

		.type = ARM64_CPUCAP_SYSTEM_FEATURE,		\



#define HWCAP_CPUID_MATCH(reg, field, s, min_value)		\

		.matches = has_cpuid_feature,			\

		.sys_reg = reg,					\

		.field_pos = field,				\

		.sign = s,					\

		.min_field_value = min_value,			\



#define __HWCAP_CAP(name, cap_type, cap)			\

		.desc = name,					\

		.type = ARM64_CPUCAP_SYSTEM_FEATURE,		\

		.hwcap_type = cap_type,				\

		.hwcap = cap,					\



#define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)	\

	{							\

		__HWCAP_CAP(#cap, cap_type, cap)		\

		HWCAP_CPUID_MATCH(reg, field, s, min_value)	\

	}



#define HWCAP_CAP_MATCH(match, cap_type, cap)			\

	{							\

		__HWCAP_CAP(#cap, cap_type, cap)		\

		.matches = match,				\

	}



static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
@@ -1387,8 +1398,35 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	{},

};



#ifdef CONFIG_COMPAT

static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)

{

	/*

	 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,

	 * in line with that of arm32 as in vfp_init(). We make sure that the

	 * check is future proof, by making sure value is non-zero.

	 */

	u32 mvfr1;



	WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());

	if (scope == SCOPE_SYSTEM)

		mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);

	else

		mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);



	return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&

		cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&

		cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);

}

#endif



static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {

#ifdef CONFIG_COMPAT

	HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),

	HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),

	/* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */

	HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),

	HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),

	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),

	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),

	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),

arch/arm64/kernel/fpsimd.c

+18 −2
Original line number Diff line number Diff line
@@ -218,6 +218,7 @@ static void sve_free(struct task_struct *task) 
static void task_fpsimd_load(void)

{

	WARN_ON(!in_softirq() && !irqs_disabled());

	WARN_ON(!system_supports_fpsimd());



	if (system_supports_sve() && test_thread_flag(TIF_SVE))

		sve_load_state(sve_pffr(&current->thread),
@@ -238,6 +239,7 @@ void fpsimd_save(void) 
	struct user_fpsimd_state *st = __this_cpu_read(fpsimd_last_state.st);

	/* set by fpsimd_bind_task_to_cpu() or fpsimd_bind_state_to_cpu() */



	WARN_ON(!system_supports_fpsimd());

	WARN_ON(!in_softirq() && !irqs_disabled());



	if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) {
@@ -977,6 +979,7 @@ void fpsimd_bind_task_to_cpu(void) 
	struct fpsimd_last_state_struct *last =

		this_cpu_ptr(&fpsimd_last_state);



	WARN_ON(!system_supports_fpsimd());

	last->st = &current->thread.uw.fpsimd_state;

	current->thread.fpsimd_cpu = smp_processor_id();
@@ -996,6 +999,7 @@ void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *st) 
	struct fpsimd_last_state_struct *last =

		this_cpu_ptr(&fpsimd_last_state);



	WARN_ON(!system_supports_fpsimd());

	WARN_ON(!in_softirq() && !irqs_disabled());



	last->st = st;
@@ -1008,8 +1012,19 @@ void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *st) 
 */

void fpsimd_restore_current_state(void)

{

	if (!system_supports_fpsimd())

	/*

	 * For the tasks that were created before we detected the absence of

	 * FP/SIMD, the TIF_FOREIGN_FPSTATE could be set via fpsimd_thread_switch(),

	 * e.g, init. This could be then inherited by the children processes.

	 * If we later detect that the system doesn't support FP/SIMD,

	 * we must clear the flag for  all the tasks to indicate that the

	 * FPSTATE is clean (as we can't have one) to avoid looping for ever in

	 * do_notify_resume().

	 */

	if (!system_supports_fpsimd()) {

		clear_thread_flag(TIF_FOREIGN_FPSTATE);

		return;

	}



	local_bh_disable();
@@ -1028,7 +1043,7 @@ void fpsimd_restore_current_state(void) 
 */

void fpsimd_update_current_state(struct user_fpsimd_state const *state)

{

	if (!system_supports_fpsimd())

	if (WARN_ON(!system_supports_fpsimd()))

		return;



	local_bh_disable();
@@ -1055,6 +1070,7 @@ void fpsimd_flush_task_state(struct task_struct *t) 


void fpsimd_flush_cpu_state(void)

{

	WARN_ON(!system_supports_fpsimd());

	__this_cpu_write(fpsimd_last_state.st, NULL);

	set_thread_flag(TIF_FOREIGN_FPSTATE);

}

arch/arm64/kernel/process.c

+7 −0
Original line number Diff line number Diff line
@@ -424,6 +424,13 @@ static void ssbs_thread_switch(struct task_struct *next) 
	if (unlikely(next->flags & PF_KTHREAD))

		return;



	/*

	 * If all CPUs implement the SSBS extension, then we just need to

	 * context-switch the PSTATE field.

	 */

	if (cpu_have_feature(cpu_feature(SSBS)))

		return;



	/* If the mitigation is enabled, then we leave SSBS clear. */

	if ((arm64_get_ssbd_state() == ARM64_SSBD_FORCE_ENABLE) ||

	    test_tsk_thread_flag(next, TIF_SSBD))