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Commit bee82ace authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: enable external voltage supply for dp phy"

parents e6d0c161 8734713d

qcom/lito-cdp.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -40,6 +40,10 @@ 
	core-supply = <&qmp_dp_phy_core_supply>;

};



&sde_dp {

	vdda-0p9-supply = <&qmp_dp_phy_core_supply>;

};



&pm7250b_vadc {

	pinctrl-0 = <

		&bmr_w_therm_default

qcom/lito-mtp.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -40,6 +40,10 @@ 
	core-supply = <&qmp_dp_phy_core_supply>;

};



&sde_dp {

	vdda-0p9-supply = <&qmp_dp_phy_core_supply>;

};



/ {

	mtp_batterydata: qcom,battery-data {

		qcom,batt-id-range-pct = <15>;

qcom/lito-sde.dtsi

+4 −6
Original line number Diff line number Diff line
@@ -483,7 +483,6 @@ 
		compatible = "qcom,dp-display";



		vdda-lp2-supply = <&L9A>;

		vdda-0p9-supply = <&L5A>;

		reg =	<0xae90000 0x0dc>,

			<0xae90200 0x0c0>,

			<0xae90400 0x508>,
@@ -506,7 +505,6 @@ 
		interrupts = <12 0>;



		clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,

			<&gcc GCC_USB3_PRIM_CLKREF_CLK>,

			<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,

			<&rpmhcc RPMH_CXO_CLK>,

			<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
@@ -517,8 +515,8 @@ 
			<&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,

			<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,

			<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;

		 clock-names = "core_aux_clk", "core_usb_ref_clk",

			"core_usb_pipe_clk", "core_usb_ref_clk_src",

		 clock-names = "core_aux_clk", "core_usb_pipe_clk",

			"core_usb_ref_clk_src",

			"link_clk", "link_iface_clk",

			"pixel_clk_rcg", "pixel_parent",

			"pixel1_clk_rcg", "pixel1_parent",
@@ -559,8 +557,8 @@ 
			qcom,phy-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-0p9";

				qcom,supply-min-voltage = <880000>;

				qcom,supply-max-voltage = <880000>;

				qcom,supply-min-voltage = <1200000>;

				qcom,supply-max-voltage = <1200000>;

				qcom,supply-enable-load = <36000>;

				qcom,supply-disable-load = <0>;

			};