Merge "ARM: dts: msm: enable mdss rscc" (e6d0c161) · Commits · e / devices / android_kernel_fairphone_FP4

qcom/lito-sde-display.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -175,7 +175,7 @@
		};

		&mdss_mdp {
		connectors = <&sde_wb &sde_dsi &sde_dsi1 &sde_dp>;
		connectors = <&sde_wb &sde_dsi &sde_dsi1 &sde_dp &sde_rscc>;
		};

		/* PHY TIMINGS REVISION W */

+0 −18

Original line number	Diff line number	Diff line
		@@ -28,7 +28,6 @@
		200000000>;
		clock-max-rate = <0 0 0 0 460000000 19200000 460000000
		460000000>;
		sde-vdd-supply = <&mdss_core_gdsc>;

		/* interrupt config */
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		@@ -230,20 +229,6 @@
		qcom,sde-dspp-dither = <0x82c 0x00010007>;
		};

		qcom,platform-supply-entries {
		#address-cells = <1>;
		#size-cells = <0>;

		qcom,platform-supply-entry@0 {
		reg = <0>;
		qcom,supply-name = "sde-vdd";
		qcom,supply-min-voltage = <0>;
		qcom,supply-max-voltage = <0>;
		qcom,supply-enable-load = <0>;
		qcom,supply-disable-load = <0>;
		};
		};

		smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
		compatible = "qcom,smmu_sde_unsec";
		iommus = <&apps_smmu 0xb40 0x402>;
		@@ -285,7 +270,6 @@
		};

		sde_rscc: qcom,sde_rscc {
		status = "disabled";
		cell-index = <0>;
		compatible = "qcom,sde-rsc";
		reg = <0xaf20000 0x3c50>,
		@@ -604,7 +588,6 @@
		cell-index = <0>;
		reg = <0xae94400 0x800>;
		reg-names = "dsi_phy";
		gdsc-supply = <&mdss_core_gdsc>;
		vdda-0p9-supply = <&L5A>;
		qcom,platform-strength-ctrl = [55 03
		55 03
		@@ -637,7 +620,6 @@
		cell-index = <1>;
		reg = <0xae96400 0x800>;
		reg-names = "dsi_phy";
		gdsc-supply = <&mdss_core_gdsc>;
		vdda-0p9-supply = <&L5A>;
		qcom,platform-strength-ctrl = [55 03
		55 03

+6 −2

Original line number	Diff line number	Diff line
		@@ -1735,13 +1735,17 @@
		<SLEEP_TCS 1>,
		<WAKE_TCS 1>,
		<CONTROL_TCS 0>;
		status = "disabled";

		msm_bus_disp_rsc {
		compatible = "qcom,msm-bus-rsc";
		qcom,msm-bus-id = <MSM_BUS_RSC_DISP>;
		status = "disabled";
		};

		sde_rsc_rpmh {
		compatible = "qcom,sde-rsc-rpmh";
		cell-index = <0>;
		};

		};

		qcom,rmtfs_sharedmem@0 {