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Commit be3a84d1 authored by Rasesh Mody's avatar Rasesh Mody Committed by David S. Miller
Browse files

bna: Brocade 1860 IOC PLL, Reg Defs and ASIC Mode Changes 



Add logic to set ASIC specfic interface in IOC, HW interface initialization
APIs, mode based initialization and MSI-X resource allocation for 1860 with
no asic block. Add new h/w specific register definitions and setup registers
used by IOC logic.

Use normal kernel declaration style, c99 initializers and const for mailbox
structures. Remove unneeded parentheses.

Signed-off-by: default avatarGurunatha Karaje <gkaraje@brocade.com>
Signed-off-by: default avatarRasesh Mody <rmody@brocade.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3869f806

drivers/net/ethernet/brocade/bna/bfa_ioc.c

+7 −1
Original line number Diff line number Diff line
@@ -1981,7 +1981,13 @@ bfa_nw_ioc_pci_init(struct bfa_ioc *ioc, struct bfa_pcidev *pcidev, 
		BUG_ON(1);

	}



	/**

	 * Set asic specific interfaces.

	 */

	if (ioc->asic_gen == BFI_ASIC_GEN_CT)

		bfa_nw_ioc_set_ct_hwif(ioc);

	else

		bfa_nw_ioc_set_ct2_hwif(ioc);



	bfa_ioc_map_port(ioc);

	bfa_ioc_reg_init(ioc);

drivers/net/ethernet/brocade/bna/bfa_ioc.h

+2 −0
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ struct bfa_ioc_regs { 
	void __iomem *hfn_mbox;

	void __iomem *lpu_mbox_cmd;

	void __iomem *lpu_mbox;

	void __iomem *lpu_read_stat;

	void __iomem *pss_ctl_reg;

	void __iomem *pss_err_status_reg;

	void __iomem *app_pll_fast_ctl_reg;
@@ -287,6 +288,7 @@ void bfa_nw_ioc_mbox_regisr(struct bfa_ioc *ioc, enum bfi_mclass mc, 
} while (0)



void bfa_nw_ioc_set_ct_hwif(struct bfa_ioc *ioc);

void bfa_nw_ioc_set_ct2_hwif(struct bfa_ioc *ioc);



void bfa_nw_ioc_attach(struct bfa_ioc *ioc, void *bfa,

		struct bfa_ioc_cbfn *cbfn);

drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c

+385 −15
Original line number Diff line number Diff line
@@ -37,7 +37,9 @@ 
static bool bfa_ioc_ct_firmware_lock(struct bfa_ioc *ioc);

static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc);

static void bfa_ioc_ct_reg_init(struct bfa_ioc *ioc);

static void bfa_ioc_ct2_reg_init(struct bfa_ioc *ioc);

static void bfa_ioc_ct_map_port(struct bfa_ioc *ioc);

static void bfa_ioc_ct2_map_port(struct bfa_ioc *ioc);

static void bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix);

static void bfa_ioc_ct_notify_fail(struct bfa_ioc *ioc);

static void bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc);
@@ -48,6 +50,9 @@ static void bfa_ioc_ct_sync_ack(struct bfa_ioc *ioc); 
static bool bfa_ioc_ct_sync_complete(struct bfa_ioc *ioc);

static enum bfa_status bfa_ioc_ct_pll_init(void __iomem *rb,

				enum bfi_asic_mode asic_mode);

static enum bfa_status bfa_ioc_ct2_pll_init(void __iomem *rb,

				enum bfi_asic_mode asic_mode);

static bool bfa_ioc_ct2_lpu_read_stat(struct bfa_ioc *ioc);



static const struct bfa_ioc_hwif nw_hwif_ct = {

	.ioc_pll_init	     = bfa_ioc_ct_pll_init,
@@ -65,6 +70,23 @@ static const struct bfa_ioc_hwif nw_hwif_ct = { 
	.ioc_sync_complete   = bfa_ioc_ct_sync_complete,

};



static const struct bfa_ioc_hwif nw_hwif_ct2 = {

	.ioc_pll_init	     = bfa_ioc_ct2_pll_init,

	.ioc_firmware_lock   = bfa_ioc_ct_firmware_lock,

	.ioc_firmware_unlock = bfa_ioc_ct_firmware_unlock,

	.ioc_reg_init	     = bfa_ioc_ct2_reg_init,

	.ioc_map_port	     = bfa_ioc_ct2_map_port,

	.ioc_lpu_read_stat   = bfa_ioc_ct2_lpu_read_stat,

	.ioc_isr_mode_set    = NULL,

	.ioc_notify_fail     = bfa_ioc_ct_notify_fail,

	.ioc_ownership_reset = bfa_ioc_ct_ownership_reset,

	.ioc_sync_start      = bfa_ioc_ct_sync_start,

	.ioc_sync_join       = bfa_ioc_ct_sync_join,

	.ioc_sync_leave	     = bfa_ioc_ct_sync_leave,

	.ioc_sync_ack	     = bfa_ioc_ct_sync_ack,

	.ioc_sync_complete   = bfa_ioc_ct_sync_complete,

};



/**

 * Called from bfa_ioc_attach() to map asic specific calls.

 */
@@ -74,6 +96,12 @@ bfa_nw_ioc_set_ct_hwif(struct bfa_ioc *ioc) 
	ioc->ioc_hwif = &nw_hwif_ct;

}



void

bfa_nw_ioc_set_ct2_hwif(struct bfa_ioc *ioc)

{

	ioc->ioc_hwif = &nw_hwif_ct2;

}



/**

 * Return true if firmware of current driver matches the running firmware.

 */
@@ -170,7 +198,11 @@ bfa_ioc_ct_notify_fail(struct bfa_ioc *ioc) 
/**

 * Host to LPU mailbox message addresses

 */

static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } ct_fnreg[] = {

static const struct {

	u32 	hfn_mbox;

	u32 	lpu_mbox;

	u32 	hfn_pgn;

} ct_fnreg[] = {

	{ HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },

	{ HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 },

	{ HOSTFN2_LPU_MBOX0_0, LPU_HOSTFN2_MBOX0_0, HOST_PAGE_NUM_FN2 },
@@ -180,7 +212,10 @@ static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } ct_fnreg[] = { 
/**

 * Host <-> LPU mailbox command/status registers - port 0

 */

static struct { u32 hfn, lpu; } ct_p0reg[] = {

static const struct {

	u32	hfn;

	u32	lpu;

} ct_p0reg[] = {

	{ HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT },

	{ HOSTFN1_LPU0_CMD_STAT, LPU0_HOSTFN1_CMD_STAT },

	{ HOSTFN2_LPU0_CMD_STAT, LPU0_HOSTFN2_CMD_STAT },
@@ -190,13 +225,32 @@ static struct { u32 hfn, lpu; } ct_p0reg[] = { 
/**

 * Host <-> LPU mailbox command/status registers - port 1

 */

static struct { u32 hfn, lpu; } ct_p1reg[] = {

static const struct {

	u32	hfn;

	u32	lpu;

} ct_p1reg[] = {

	{ HOSTFN0_LPU1_CMD_STAT, LPU1_HOSTFN0_CMD_STAT },

	{ HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT },

	{ HOSTFN2_LPU1_CMD_STAT, LPU1_HOSTFN2_CMD_STAT },

	{ HOSTFN3_LPU1_CMD_STAT, LPU1_HOSTFN3_CMD_STAT }

};



static const struct {

	u32	hfn_mbox;

	u32	lpu_mbox;

	u32	hfn_pgn;

	u32	hfn;

	u32	lpu;

	u32	lpu_read;

} ct2_reg[] = {

	{ CT2_HOSTFN_LPU0_MBOX0, CT2_LPU0_HOSTFN_MBOX0, CT2_HOSTFN_PAGE_NUM,

	  CT2_HOSTFN_LPU0_CMD_STAT, CT2_LPU0_HOSTFN_CMD_STAT,

	  CT2_HOSTFN_LPU0_READ_STAT},

	{ CT2_HOSTFN_LPU1_MBOX0, CT2_LPU1_HOSTFN_MBOX0, CT2_HOSTFN_PAGE_NUM,

	  CT2_HOSTFN_LPU1_CMD_STAT, CT2_LPU1_HOSTFN_CMD_STAT,

	  CT2_HOSTFN_LPU1_READ_STAT},

};



static void

bfa_ioc_ct_reg_init(struct bfa_ioc *ioc)

{
@@ -218,8 +272,8 @@ bfa_ioc_ct_reg_init(struct bfa_ioc *ioc) 
		ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;

		ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1;

	} else {

		ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);

		ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);

		ioc->ioc_regs.heartbeat = rb + BFA_IOC1_HBEAT_REG;

		ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC1_STATE_REG;

		ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG;

		ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p1reg[pcifn].hfn;

		ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p1reg[pcifn].lpu;
@@ -230,24 +284,24 @@ bfa_ioc_ct_reg_init(struct bfa_ioc *ioc) 
	/*

	 * PSS control registers

	 */

	ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);

	ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);

	ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG);

	ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG);

	ioc->ioc_regs.pss_ctl_reg = rb + PSS_CTL_REG;

	ioc->ioc_regs.pss_err_status_reg = rb + PSS_ERR_STATUS_REG;

	ioc->ioc_regs.app_pll_fast_ctl_reg = rb + APP_PLL_LCLK_CTL_REG;

	ioc->ioc_regs.app_pll_slow_ctl_reg = rb + APP_PLL_SCLK_CTL_REG;



	/*

	 * IOC semaphore registers and serialization

	 */

	ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);

	ioc->ioc_regs.ioc_usage_sem_reg = (rb + HOST_SEM1_REG);

	ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);

	ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT);

	ioc->ioc_regs.ioc_fail_sync = (rb + BFA_IOC_FAIL_SYNC);

	ioc->ioc_regs.ioc_sem_reg = rb + HOST_SEM0_REG;

	ioc->ioc_regs.ioc_usage_sem_reg = rb + HOST_SEM1_REG;

	ioc->ioc_regs.ioc_init_sem_reg = rb + HOST_SEM2_REG;

	ioc->ioc_regs.ioc_usage_reg = rb + BFA_FW_USE_COUNT;

	ioc->ioc_regs.ioc_fail_sync = rb + BFA_IOC_FAIL_SYNC;



	/**

	 * sram memory access

	 */

	ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);

	ioc->ioc_regs.smem_page_start = rb + PSS_SMEM_PAGE_START;

	ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CT;



	/*
@@ -256,6 +310,64 @@ bfa_ioc_ct_reg_init(struct bfa_ioc *ioc) 
	ioc->ioc_regs.err_set = (rb + ERR_SET_REG);

}



static void

bfa_ioc_ct2_reg_init(struct bfa_ioc *ioc)

{

	void __iomem *rb;

	int		port = bfa_ioc_portid(ioc);



	rb = bfa_ioc_bar0(ioc);



	ioc->ioc_regs.hfn_mbox = rb + ct2_reg[port].hfn_mbox;

	ioc->ioc_regs.lpu_mbox = rb + ct2_reg[port].lpu_mbox;

	ioc->ioc_regs.host_page_num_fn = rb + ct2_reg[port].hfn_pgn;

	ioc->ioc_regs.hfn_mbox_cmd = rb + ct2_reg[port].hfn;

	ioc->ioc_regs.lpu_mbox_cmd = rb + ct2_reg[port].lpu;

	ioc->ioc_regs.lpu_read_stat = rb + ct2_reg[port].lpu_read;



	if (port == 0) {

		ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC0_HBEAT_REG;

		ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG;

		ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG;

		ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;

		ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1;

	} else {

		ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC1_HBEAT_REG;

		ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG;

		ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG;

		ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;

		ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0;

	}



	/*

	 * PSS control registers

	 */

	ioc->ioc_regs.pss_ctl_reg = rb + PSS_CTL_REG;

	ioc->ioc_regs.pss_err_status_reg = rb + PSS_ERR_STATUS_REG;

	ioc->ioc_regs.app_pll_fast_ctl_reg = rb + CT2_APP_PLL_LCLK_CTL_REG;

	ioc->ioc_regs.app_pll_slow_ctl_reg = rb + CT2_APP_PLL_SCLK_CTL_REG;



	/*

	 * IOC semaphore registers and serialization

	 */

	ioc->ioc_regs.ioc_sem_reg = rb + CT2_HOST_SEM0_REG;

	ioc->ioc_regs.ioc_usage_sem_reg = rb + CT2_HOST_SEM1_REG;

	ioc->ioc_regs.ioc_init_sem_reg = rb + CT2_HOST_SEM2_REG;

	ioc->ioc_regs.ioc_usage_reg = rb + CT2_BFA_FW_USE_COUNT;

	ioc->ioc_regs.ioc_fail_sync = rb + CT2_BFA_IOC_FAIL_SYNC;



	/**

	 * sram memory access

	 */

	ioc->ioc_regs.smem_page_start = rb + PSS_SMEM_PAGE_START;

	ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CT;



	/*

	 * err set reg : for notification of hb failure in fcmode

	 */

	ioc->ioc_regs.err_set = rb + ERR_SET_REG;

}



/**

 * Initialize IOC to port mapping.

 */
@@ -276,6 +388,16 @@ bfa_ioc_ct_map_port(struct bfa_ioc *ioc) 


}



static void

bfa_ioc_ct2_map_port(struct bfa_ioc *ioc)

{

	void __iomem *rb = ioc->pcidev.pci_bar_kva;

	u32	r32;



	r32 = readl(rb + CT2_HOSTFN_PERSONALITY0);

	ioc->port_id = ((r32 & __FC_LL_PORT_MAP__MK) >> __FC_LL_PORT_MAP__SH);

}



/**

 * Set interrupt mode for a function: INTX or MSIX

 */
@@ -307,6 +429,50 @@ bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix) 
	writel(r32, rb + FNC_PERS_REG);

}



static bool

bfa_ioc_ct2_lpu_read_stat(struct bfa_ioc *ioc)

{

	u32 r32;



	r32 = readl(ioc->ioc_regs.lpu_read_stat);

	if (r32) {

		writel(1, ioc->ioc_regs.lpu_read_stat);

		return true;

	}



	return false;

}



/**

 * MSI-X resource allocation for 1860 with no asic block

 */

#define HOSTFN_MSIX_DEFAULT		64

#define HOSTFN_MSIX_VT_INDEX_MBOX_ERR	0x30138

#define HOSTFN_MSIX_VT_OFST_NUMVT	0x3013c

#define __MSIX_VT_NUMVT__MK		0x003ff800

#define __MSIX_VT_NUMVT__SH		11

#define __MSIX_VT_NUMVT_(_v)		((_v) << __MSIX_VT_NUMVT__SH)

#define __MSIX_VT_OFST_			0x000007ff

void

bfa_ioc_ct2_poweron(struct bfa_ioc *ioc)

{

	void __iomem *rb = ioc->pcidev.pci_bar_kva;

	u32 r32;



	r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT);

	if (r32 & __MSIX_VT_NUMVT__MK) {

		writel(r32 & __MSIX_VT_OFST_,

			rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR);

		return;

	}



	writel(__MSIX_VT_NUMVT_(HOSTFN_MSIX_DEFAULT - 1) |

			HOSTFN_MSIX_DEFAULT * bfa_ioc_pcifn(ioc),

			rb + HOSTFN_MSIX_VT_OFST_NUMVT);

	writel(HOSTFN_MSIX_DEFAULT * bfa_ioc_pcifn(ioc),

			rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR);

}



/**

 * Cleanup hw semaphore and usecnt registers

 */
@@ -499,3 +665,207 @@ bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode) 
	writel(0, (rb + MBIST_CTL_REG));

	return BFA_STATUS_OK;

}



static void

bfa_ioc_ct2_sclk_init(void __iomem *rb)

{

	u32 r32;



	/*

	 * put s_clk PLL and PLL FSM in reset

	 */

	r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));

	r32 &= ~(__APP_PLL_SCLK_ENABLE | __APP_PLL_SCLK_LRESETN);

	r32 |= (__APP_PLL_SCLK_ENARST | __APP_PLL_SCLK_BYPASS |

		__APP_PLL_SCLK_LOGIC_SOFT_RESET);

	writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));



	/*

	 * Ignore mode and program for the max clock (which is FC16)

	 * Firmware/NFC will do the PLL init appropiately

	 */

	r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));

	r32 &= ~(__APP_PLL_SCLK_REFCLK_SEL | __APP_PLL_SCLK_CLK_DIV2);

	writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));



	/*

	 * while doing PLL init dont clock gate ethernet subsystem

	 */

	r32 = readl((rb + CT2_CHIP_MISC_PRG));

	writel((r32 | __ETH_CLK_ENABLE_PORT0),

				(rb + CT2_CHIP_MISC_PRG));



	r32 = readl((rb + CT2_PCIE_MISC_REG));

	writel((r32 | __ETH_CLK_ENABLE_PORT1),

				(rb + CT2_PCIE_MISC_REG));



	/*

	 * set sclk value

	 */

	r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));

	r32 &= (__P_SCLK_PLL_LOCK | __APP_PLL_SCLK_REFCLK_SEL |

		__APP_PLL_SCLK_CLK_DIV2);

	writel(r32 | 0x1061731b, (rb + CT2_APP_PLL_SCLK_CTL_REG));



	/*

	 * poll for s_clk lock or delay 1ms

	 */

	udelay(1000);



	/*

	 * Dont do clock gating for ethernet subsystem, firmware/NFC will

	 * do this appropriately

	 */

}



static void

bfa_ioc_ct2_lclk_init(void __iomem *rb)

{

	u32 r32;



	/*

	 * put l_clk PLL and PLL FSM in reset

	 */

	r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));

	r32 &= ~(__APP_PLL_LCLK_ENABLE | __APP_PLL_LCLK_LRESETN);

	r32 |= (__APP_PLL_LCLK_ENARST | __APP_PLL_LCLK_BYPASS |

		__APP_PLL_LCLK_LOGIC_SOFT_RESET);

	writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));



	/*

	 * set LPU speed (set for FC16 which will work for other modes)

	 */

	r32 = readl((rb + CT2_CHIP_MISC_PRG));

	writel(r32, (rb + CT2_CHIP_MISC_PRG));



	/*

	 * set LPU half speed (set for FC16 which will work for other modes)

	 */

	r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));

	writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));



	/*

	 * set lclk for mode (set for FC16)

	 */

	r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));

	r32 &= (__P_LCLK_PLL_LOCK | __APP_LPUCLK_HALFSPEED);

	r32 |= 0x20c1731b;

	writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));



	/*

	 * poll for s_clk lock or delay 1ms

	 */

	udelay(1000);

}



static void

bfa_ioc_ct2_mem_init(void __iomem *rb)

{

	u32 r32;



	r32 = readl((rb + PSS_CTL_REG));

	r32 &= ~__PSS_LMEM_RESET;

	writel(r32, (rb + PSS_CTL_REG));

	udelay(1000);



	writel(__EDRAM_BISTR_START, (rb + CT2_MBIST_CTL_REG));

	udelay(1000);

	writel(0, (rb + CT2_MBIST_CTL_REG));

}



static void

bfa_ioc_ct2_mac_reset(void __iomem *rb)

{

	volatile u32 r32;



	bfa_ioc_ct2_sclk_init(rb);

	bfa_ioc_ct2_lclk_init(rb);



	/*

	 * release soft reset on s_clk & l_clk

	 */

	r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));

	writel((r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET),

			(rb + CT2_APP_PLL_SCLK_CTL_REG));



	/*

	 * release soft reset on s_clk & l_clk

	 */

	r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));

	writel((r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET),

			(rb + CT2_APP_PLL_LCLK_CTL_REG));



	/* put port0, port1 MAC & AHB in reset */

	writel((__CSI_MAC_RESET | __CSI_MAC_AHB_RESET),

			(rb + CT2_CSI_MAC_CONTROL_REG(0)));

	writel((__CSI_MAC_RESET | __CSI_MAC_AHB_RESET),

			(rb + CT2_CSI_MAC_CONTROL_REG(1)));

}



#define CT2_NFC_MAX_DELAY       1000

static enum bfa_status

bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode)

{

	volatile u32 wgn, r32;

	int i;



	/*

	 * Initialize PLL if not already done by NFC

	 */

	wgn = readl(rb + CT2_WGN_STATUS);

	if (!(wgn & __GLBL_PF_VF_CFG_RDY)) {

		writel(__HALT_NFC_CONTROLLER, (rb + CT2_NFC_CSR_SET_REG));

		for (i = 0; i < CT2_NFC_MAX_DELAY; i++) {

			r32 = readl(rb + CT2_NFC_CSR_SET_REG);

			if (r32 & __NFC_CONTROLLER_HALTED)

				break;

			udelay(1000);

		}

	}



	/*

	 * Mask the interrupts and clear any

	 * pending interrupts left by BIOS/EFI

	 */



	writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK));

	writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK));



	r32 = readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));

	if (r32 == 1) {

		writel(1, (rb + CT2_LPU0_HOSTFN_CMD_STAT));

		readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));

	}

	r32 = readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));

	if (r32 == 1) {

		writel(1, (rb + CT2_LPU1_HOSTFN_CMD_STAT));

		readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));

	}



	bfa_ioc_ct2_mac_reset(rb);

	bfa_ioc_ct2_sclk_init(rb);

	bfa_ioc_ct2_lclk_init(rb);



	/*

	 * release soft reset on s_clk & l_clk

	 */

	r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));

	writel((r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET),

			(rb + CT2_APP_PLL_SCLK_CTL_REG));



	/*

	 * Announce flash device presence, if flash was corrupted.

	 */

	if (wgn == (__WGN_READY | __GLBL_PF_VF_CFG_RDY)) {

		r32 = readl((rb + PSS_GPIO_OUT_REG));

		writel((r32 & ~1), (rb + PSS_GPIO_OUT_REG));

		r32 = readl((rb + PSS_GPIO_OE_REG));

		writel((r32 | 1), (rb + PSS_GPIO_OE_REG));

	}



	bfa_ioc_ct2_mem_init(rb);



	writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG));

	writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG));

	return BFA_STATUS_OK;

}