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Commit 3869f806 authored by David S. Miller's avatar David S. Miller
Browse files

Merge git://github.com/Jkirsher/net-next

parents f9b491ec 0ccb974d

drivers/net/ethernet/intel/e1000/e1000_main.c

+3 −3
Original line number Diff line number Diff line
@@ -1814,8 +1814,8 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter) 


	rctl &= ~(3 << E1000_RCTL_MO_SHIFT);



	rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |

		E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |

	rctl |= E1000_RCTL_BAM | E1000_RCTL_LBM_NO |

		E1000_RCTL_RDMTS_HALF |

		(hw->mc_filter_type << E1000_RCTL_MO_SHIFT);



	if (hw->tbi_compatibility_on == 1)
@@ -1917,7 +1917,7 @@ static void e1000_configure_rx(struct e1000_adapter *adapter) 
	}



	/* Enable Receives */

	ew32(RCTL, rctl);

	ew32(RCTL, rctl | E1000_RCTL_EN);

}



/**

drivers/net/ethernet/intel/ixgbe/ixgbe.h

+14 −11
Original line number Diff line number Diff line
@@ -301,26 +301,29 @@ struct ixgbe_ring_container { 
 */

struct ixgbe_q_vector {

	struct ixgbe_adapter *adapter;

	unsigned int v_idx; /* index of q_vector within array, also used for

	                     * finding the bit in EICR and friends that

	                     * represents the vector for this ring */

#ifdef CONFIG_IXGBE_DCA

	int cpu;	    /* CPU for DCA */

#endif

	struct napi_struct napi;

	u16 v_idx;		/* index of q_vector within array, also used for

				 * finding the bit in EICR and friends that

				 * represents the vector for this ring */

	u16 itr;		/* Interrupt throttle rate written to EITR */

	struct ixgbe_ring_container rx, tx;

	u32 eitr;



	struct napi_struct napi;

	cpumask_var_t affinity_mask;

	char name[IFNAMSIZ + 9];

};



/* Helper macros to switch between ints/sec and what the register uses.

 * And yes, it's the same math going both ways.  The lowest value

 * supported by all of the ixgbe hardware is 8.

/*

 * microsecond values for various ITR rates shifted by 2 to fit itr register

 * with the first 3 bits reserved 0

 */

#define EITR_INTS_PER_SEC_TO_REG(_eitr) \

	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)

#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG

#define IXGBE_MIN_RSC_ITR	24

#define IXGBE_100K_ITR		40

#define IXGBE_20K_ITR		200

#define IXGBE_10K_ITR		400

#define IXGBE_8K_ITR		500



static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)

{

drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c

+2 −6
Original line number Diff line number Diff line
@@ -358,7 +358,6 @@ static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) 
	u32 fctrl_reg;

	u32 rmcs_reg;

	u32 reg;

	u32 rx_pba_size;

	u32 link_speed = 0;

	bool link_up;
@@ -461,16 +460,13 @@ static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) 


	/* Set up and enable Rx high/low water mark thresholds, enable XON. */

	if (hw->fc.current_mode & ixgbe_fc_tx_pause) {

		rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));

		rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;



		reg = (rx_pba_size - hw->fc.low_water) << 6;

		reg = hw->fc.low_water << 6;

		if (hw->fc.send_xon)

			reg |= IXGBE_FCRTL_XONE;



		IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg);



		reg = (rx_pba_size - hw->fc.high_water) << 6;

		reg = hw->fc.high_water[packetbuf_num] << 6;

		reg |= IXGBE_FCRTH_FCEN;



		IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg);

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

+5 −7
Original line number Diff line number Diff line
@@ -1932,7 +1932,6 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num) 
	s32 ret_val = 0;

	u32 mflcn_reg, fccfg_reg;

	u32 reg;

	u32 rx_pba_size;

	u32 fcrtl, fcrth;



#ifdef CONFIG_DCB
@@ -2012,11 +2011,8 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num) 
	IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);

	IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);



	rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));

	rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;



	fcrth = (rx_pba_size - hw->fc.high_water) << 10;

	fcrtl = (rx_pba_size - hw->fc.low_water) << 10;

	fcrth = hw->fc.high_water[packetbuf_num] << 10;

	fcrtl = hw->fc.low_water << 10;



	if (hw->fc.current_mode & ixgbe_fc_tx_pause) {

		fcrth |= IXGBE_FCRTH_FCEN;
@@ -2293,7 +2289,9 @@ static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) 
	 * Validate the water mark configuration.  Zero water marks are invalid

	 * because it causes the controller to just blast out fc packets.

	 */

	if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {

	if (!hw->fc.low_water ||

	    !hw->fc.high_water[packetbuf_num] ||

	    !hw->fc.pause_time) {

		hw_dbg(hw, "Invalid water mark configuration\n");

		ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;

		goto out;

drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.h

+0 −1
Original line number Diff line number Diff line
@@ -36,7 +36,6 @@ 


#define IXGBE_MAX_PACKET_BUFFERS 8

#define MAX_USER_PRIORITY        8

#define MAX_TRAFFIC_CLASS        8

#define MAX_BW_GROUP             8

#define BW_PERCENT               100