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Commit bba9b3ec authored by NeilBrown's avatar NeilBrown Committed by Greg Kroah-Hartman
Browse files

staging: mt7621-pci: remove conditional compilation. 



Code currently defines:

#define CONFIG_PCIE_PORT0
#define CONFIG_PCIE_PORT1
#define CONFIG_PCIE_PORT2
#define GPIO_PERST

and then compiles code only if they are defined.
We might want to disable some of these via devicetree one
day, but for now just remove the #defines and the
conditions - all the code for different ports is
easy to identify.

Signed-off-by: default avatarNeilBrown <neil@brown.name>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent d4e3a1f6

drivers/staging/mt7621-pci/pci-mt7621.c

+15 −55
Original line number Original line Diff line number Diff line
@@ -64,9 +64,6 @@ extern void chk_phy_pll(void); 
 * devices.

 * devices.

 */

 */





#define CONFIG_PCIE_PORT0

#define CONFIG_PCIE_PORT1

#define CONFIG_PCIE_PORT2

#define RALINK_PCIE0_CLK_EN		(1<<24)

#define RALINK_PCIE0_CLK_EN		(1<<24)

#define RALINK_PCIE1_CLK_EN		(1<<25)

#define RALINK_PCIE1_CLK_EN		(1<<25)

#define RALINK_PCIE2_CLK_EN		(1<<26)

#define RALINK_PCIE2_CLK_EN		(1<<26)
@@ -140,7 +137,7 @@ extern void chk_phy_pll(void); 
#define RALINK_PCI_IO_MAP_BASE		0x1e160000

#define RALINK_PCI_IO_MAP_BASE		0x1e160000





#define RALINK_SYSTEM_CONTROL_BASE	0xbe000000

#define RALINK_SYSTEM_CONTROL_BASE	0xbe000000

#define GPIO_PERST



#define ASSERT_SYSRST_PCIE(val)		\

#define ASSERT_SYSRST_PCIE(val)		\

	do {								\

	do {								\

		if (*(unsigned int *)(0xbe00000c) == 0x00030101)	\

		if (*(unsigned int *)(0xbe00000c) == 0x00030101)	\
@@ -392,21 +389,15 @@ set_pcie_phy(u32 *addr, int start_b, int bits, int val) 
void

void

bypass_pipe_rst(void)

bypass_pipe_rst(void)

{

{

#if defined (CONFIG_PCIE_PORT0)

	/* PCIe Port 0 */

	/* PCIe Port 0 */

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]

#endif

#if defined (CONFIG_PCIE_PORT1)

	/* PCIe Port 1 */

	/* PCIe Port 1 */

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]

#endif

#if defined (CONFIG_PCIE_PORT2)

	/* PCIe Port 2 */

	/* PCIe Port 2 */

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]

#endif

}

}





void

void
@@ -415,7 +406,6 @@ set_phy_for_ssc(void) 
	unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));

	unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));





	reg = (reg >> 6) & 0x7;

	reg = (reg >> 6) & 0x7;

#if defined (CONFIG_PCIE_PORT0) || defined (CONFIG_PCIE_PORT1)

	/* Set PCIe Port0 & Port1 PHY to disable SSC */

	/* Set PCIe Port0 & Port1 PHY to disable SSC */

	/* Debug Xtal Type */

	/* Debug Xtal Type */

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
@@ -456,8 +446,7 @@ set_phy_for_ssc(void) 
	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 1 enable

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 1 enable

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 1 disable control

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 1 disable control

#endif



#if defined (CONFIG_PCIE_PORT2)

	/* Set PCIe Port2 PHY to disable SSC */

	/* Set PCIe Port2 PHY to disable SSC */

	/* Debug Xtal Type */

	/* Debug Xtal Type */

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
@@ -490,7 +479,6 @@ set_phy_for_ssc(void) 
	/* Enable PHY and disable force mode */

	/* Enable PHY and disable force mode */

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control

	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control

#endif

}

}





void setup_cm_memory_region(struct resource *mem_resource)

void setup_cm_memory_region(struct resource *mem_resource)
@@ -519,18 +507,13 @@ static int mt7621_pci_probe(struct platform_device *pdev) 
	ioport_resource.start= 0;

	ioport_resource.start= 0;

	ioport_resource.end = ~0;

	ioport_resource.end = ~0;





#if defined (CONFIG_PCIE_PORT0)

	val = RALINK_PCIE0_RST;

	val = RALINK_PCIE0_RST;

#endif

#if defined (CONFIG_PCIE_PORT1)

	val |= RALINK_PCIE1_RST;

	val |= RALINK_PCIE1_RST;

#endif

#if defined (CONFIG_PCIE_PORT2)

	val |= RALINK_PCIE2_RST;

	val |= RALINK_PCIE2_RST;

#endif



	ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);

	ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);

	printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);

	printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);

#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/



	*(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);

	*(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);

	*(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;

	*(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;

	mdelay(100);

	mdelay(100);
@@ -539,18 +522,11 @@ static int mt7621_pci_probe(struct platform_device *pdev) 
	*(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7);		// clear DATA

	*(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7);		// clear DATA





	mdelay(100);

	mdelay(100);

#else



	*(unsigned int *)(0xbe000060) &= ~0x00000c00;

#endif

#if defined (CONFIG_PCIE_PORT0)

	val = RALINK_PCIE0_RST;

	val = RALINK_PCIE0_RST;

#endif

#if defined (CONFIG_PCIE_PORT1)

	val |= RALINK_PCIE1_RST;

	val |= RALINK_PCIE1_RST;

#endif

#if defined (CONFIG_PCIE_PORT2)

	val |= RALINK_PCIE2_RST;

	val |= RALINK_PCIE2_RST;

#endif



	DEASSERT_SYSRST_PCIE(val);

	DEASSERT_SYSRST_PCIE(val);

	printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);

	printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
@@ -559,18 +535,14 @@ static int mt7621_pci_probe(struct platform_device *pdev) 
	set_phy_for_ssc();

	set_phy_for_ssc();

	printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);

	printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);





#if defined (CONFIG_PCIE_PORT0)

	read_config(0, 0, 0, 0x70c, &val);

	read_config(0, 0, 0, 0x70c, &val);

	printk("Port 0 N_FTS = %x\n", (unsigned int)val);

	printk("Port 0 N_FTS = %x\n", (unsigned int)val);

#endif



#if defined (CONFIG_PCIE_PORT1)

	read_config(0, 1, 0, 0x70c, &val);

	read_config(0, 1, 0, 0x70c, &val);

	printk("Port 1 N_FTS = %x\n", (unsigned int)val);

	printk("Port 1 N_FTS = %x\n", (unsigned int)val);

#endif



#if defined (CONFIG_PCIE_PORT2)

	read_config(0, 2, 0, 0x70c, &val);

	read_config(0, 2, 0, 0x70c, &val);

	printk("Port 2 N_FTS = %x\n", (unsigned int)val);

	printk("Port 2 N_FTS = %x\n", (unsigned int)val);

#endif





	RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);

	RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);

	RALINK_SYSCFG1 &= ~(0x30);

	RALINK_SYSCFG1 &= ~(0x30);
@@ -582,16 +554,10 @@ static int mt7621_pci_probe(struct platform_device *pdev) 
	mdelay(50);

	mdelay(50);

	RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);

	RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);





#if defined GPIO_PERST /* add GPIO control instead of PERST_N */  /*chhung*/

	/* Use GPIO control instead of PERST_N */

	*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;		// set DATA

	*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;		// set DATA

	mdelay(100);

	mdelay(1000);

#else

	RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST

#endif

	mdelay(500);





	mdelay(500);

#if defined (CONFIG_PCIE_PORT0)

	if(( RALINK_PCI0_STATUS & 0x1) == 0)

	if(( RALINK_PCI0_STATUS & 0x1) == 0)

	{

	{

		printk("PCIE0 no card, disable it(RST&CLK)\n");

		printk("PCIE0 no card, disable it(RST&CLK)\n");
@@ -602,8 +568,7 @@ static int mt7621_pci_probe(struct platform_device *pdev) 
		pcie_link_status |= 1<<0;

		pcie_link_status |= 1<<0;

		RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt

		RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt

	}

	}

#endif



#if defined (CONFIG_PCIE_PORT1)

	if(( RALINK_PCI1_STATUS & 0x1) == 0)

	if(( RALINK_PCI1_STATUS & 0x1) == 0)

	{

	{

		printk("PCIE1 no card, disable it(RST&CLK)\n");

		printk("PCIE1 no card, disable it(RST&CLK)\n");
@@ -614,8 +579,7 @@ static int mt7621_pci_probe(struct platform_device *pdev) 
		pcie_link_status |= 1<<1;

		pcie_link_status |= 1<<1;

		RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt

		RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt

	}

	}

#endif



#if defined (CONFIG_PCIE_PORT2)

	if (( RALINK_PCI2_STATUS & 0x1) == 0) {

	if (( RALINK_PCI2_STATUS & 0x1) == 0) {

		printk("PCIE2 no card, disable it(RST&CLK)\n");

		printk("PCIE2 no card, disable it(RST&CLK)\n");

		ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);

		ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
@@ -625,7 +589,7 @@ static int mt7621_pci_probe(struct platform_device *pdev) 
		pcie_link_status |= 1<<2;

		pcie_link_status |= 1<<2;

		RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt

		RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt

	}

	}

#endif



	if (pcie_link_status == 0)

	if (pcie_link_status == 0)

		return 0;

		return 0;
@@ -676,7 +640,6 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num 
	RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;

	RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;

	RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;

	RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;





#if defined (CONFIG_PCIE_PORT0)

	//PCIe0

	//PCIe0

	if((pcie_link_status & 0x1) != 0) {

	if((pcie_link_status & 0x1) != 0) {

		RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE

		RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE
@@ -684,8 +647,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num 
		RALINK_PCI0_CLASS = 0x06040001;

		RALINK_PCI0_CLASS = 0x06040001;

		printk("PCIE0 enabled\n");

		printk("PCIE0 enabled\n");

	}

	}

#endif



#if defined (CONFIG_PCIE_PORT1)

	//PCIe1

	//PCIe1

	if ((pcie_link_status & 0x2) != 0) {

	if ((pcie_link_status & 0x2) != 0) {

		RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE

		RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE
@@ -693,8 +655,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num 
		RALINK_PCI1_CLASS = 0x06040001;

		RALINK_PCI1_CLASS = 0x06040001;

		printk("PCIE1 enabled\n");

		printk("PCIE1 enabled\n");

	}

	}

#endif



#if defined (CONFIG_PCIE_PORT2)

	//PCIe2

	//PCIe2

	if ((pcie_link_status & 0x4) != 0) {

	if ((pcie_link_status & 0x4) != 0) {

		RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE

		RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE
@@ -702,7 +663,6 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num 
		RALINK_PCI2_CLASS = 0x06040001;

		RALINK_PCI2_CLASS = 0x06040001;

		printk("PCIE2 enabled\n");

		printk("PCIE2 enabled\n");

	}

	}

#endif





	switch(pcie_link_status) {

	switch(pcie_link_status) {

	case 7:

	case 7: