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Commit d4e3a1f6 authored by NeilBrown's avatar NeilBrown Committed by Greg Kroah-Hartman
Browse files

staging: mt7621-pci: white-space cleanups. 



- remove white space at end of line.
- no more than 2 blank line at a time
- remove spaces before tabs
- use tabs to line things up
- re-indent some #define do{}while(0)

Signed-off-by: default avatarNeilBrown <neil@brown.name>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 46d09312

drivers/staging/mt7621-pci/pci-mt7621.c

+143 −148
Original line number Original line Diff line number Diff line
@@ -119,7 +119,6 @@ extern void chk_phy_pll(void); 
#define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)

#define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)

#define RALINK_PCIEPHY_P2_CTL_OFFSET	(RALINK_PCI_BASE + 0xA000)

#define RALINK_PCIEPHY_P2_CTL_OFFSET	(RALINK_PCI_BASE + 0xA000)







#define MV_WRITE(ofs, data)	\

#define MV_WRITE(ofs, data)	\

	*(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)

	*(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)

#define MV_READ(ofs, data)	\

#define MV_READ(ofs, data)	\
@@ -137,20 +136,20 @@ extern void chk_phy_pll(void); 
#define MV_READ_8(ofs, data)	\

#define MV_READ_8(ofs, data)	\

	*(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))

	*(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))









#define RALINK_PCI_MM_MAP_BASE		0x60000000

#define RALINK_PCI_MM_MAP_BASE		0x60000000

#define RALINK_PCI_IO_MAP_BASE		0x1e160000

#define RALINK_PCI_IO_MAP_BASE		0x1e160000





#define RALINK_SYSTEM_CONTROL_BASE	0xbe000000

#define RALINK_SYSTEM_CONTROL_BASE	0xbe000000

#define GPIO_PERST

#define GPIO_PERST

#define ASSERT_SYSRST_PCIE(val)		do {	\

#define ASSERT_SYSRST_PCIE(val)		\

	do {								\

		if (*(unsigned int *)(0xbe00000c) == 0x00030101)	\

		if (*(unsigned int *)(0xbe00000c) == 0x00030101)	\

			RALINK_RSTCTRL |= val;				\

			RALINK_RSTCTRL |= val;				\

		else							\

		else							\

			RALINK_RSTCTRL &= ~val;				\

			RALINK_RSTCTRL &= ~val;				\

	} while(0)

	} while(0)

#define DEASSERT_SYSRST_PCIE(val) 	do {	\

#define DEASSERT_SYSRST_PCIE(val)	\

	do {								\

		if (*(unsigned int *)(0xbe00000c) == 0x00030101)	\

		if (*(unsigned int *)(0xbe00000c) == 0x00030101)	\

			RALINK_RSTCTRL &= ~val;				\

			RALINK_RSTCTRL &= ~val;				\

		else							\

		else							\
@@ -275,7 +274,6 @@ write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val) 
	return PCIBIOS_SUCCESSFUL;

	return PCIBIOS_SUCCESSFUL;

}

}







static int

static int

pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)

pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)

{

{
@@ -313,6 +311,7 @@ static struct resource mt7621_res_pci_mem1 = { 
	.end		= (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),

	.end		= (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),

	.flags		= IORESOURCE_MEM,

	.flags		= IORESOURCE_MEM,

};

};



static struct resource mt7621_res_pci_io1 = {

static struct resource mt7621_res_pci_io1 = {

	.name		= "PCI I/O1",

	.name		= "PCI I/O1",

	.start		= RALINK_PCI_IO_MAP_BASE,

	.start		= RALINK_PCI_IO_MAP_BASE,
@@ -355,7 +354,6 @@ write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned 
	return;

	return;

}

}







int

int

pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

{

{
@@ -500,8 +498,8 @@ void setup_cm_memory_region(struct resource *mem_resource) 
	resource_size_t mask;

	resource_size_t mask;

	if (mips_cps_numiocu(0)) {

	if (mips_cps_numiocu(0)) {

		/* FIXME: hardware doesn't accept mask values with 1s after

		/* FIXME: hardware doesn't accept mask values with 1s after

		   0s (e.g. 0xffef), so it would be great to warn if that's

		 * 0s (e.g. 0xffef), so it would be great to warn if that's

		   about to happen */

		 * about to happen */

		mask = ~(mem_resource->end - mem_resource->start);

		mask = ~(mem_resource->end - mem_resource->start);





		write_gcr_reg1_base(mem_resource->start);

		write_gcr_reg1_base(mem_resource->start);
@@ -584,7 +582,6 @@ static int mt7621_pci_probe(struct platform_device *pdev) 
	mdelay(50);

	mdelay(50);

	RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);

	RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);







#if defined GPIO_PERST /* add GPIO control instead of PERST_N */  /*chhung*/

#if defined GPIO_PERST /* add GPIO control instead of PERST_N */  /*chhung*/

	*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;		// set DATA

	*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;		// set DATA

	mdelay(100);

	mdelay(100);
@@ -593,7 +590,6 @@ static int mt7621_pci_probe(struct platform_device *pdev) 
#endif

#endif

	mdelay(500);

	mdelay(500);







	mdelay(500);

	mdelay(500);

#if defined (CONFIG_PCIE_PORT0)

#if defined (CONFIG_PCIE_PORT0)

	if(( RALINK_PCI0_STATUS & 0x1) == 0)

	if(( RALINK_PCI0_STATUS & 0x1) == 0)
@@ -708,7 +704,6 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num 
	}

	}

#endif

#endif







	switch(pcie_link_status) {

	switch(pcie_link_status) {

	case 7:

	case 7:

		read_config(0, 2, 0, 0x4, &val);

		read_config(0, 2, 0, 0x4, &val);