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Commit b90dc392 authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Bjorn Helgaas
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PCI: dwc: designware: Move register defines to designware header file 



No functional change. Move the register defines and other macros from
pcie-designware.c to pcie-designware.h. This is in preparation to split the
pcie-designware.c file into designware core file and host-specific file.

While at that also fix a checkpatch warning.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-By: default avatarJoao Pinto <jpinto@synopsys.com>
parent 11a61a86

drivers/pci/dwc/pcie-designware.c

+0 −70
Original line number Diff line number Diff line
@@ -25,76 +25,6 @@ 


#include "pcie-designware.h"



/* Parameters for the waiting for link up routine */

#define LINK_WAIT_MAX_RETRIES		10

#define LINK_WAIT_USLEEP_MIN		90000

#define LINK_WAIT_USLEEP_MAX		100000



/* Parameters for the waiting for iATU enabled routine */

#define LINK_WAIT_MAX_IATU_RETRIES	5

#define LINK_WAIT_IATU_MIN		9000

#define LINK_WAIT_IATU_MAX		10000



/* Synopsys-specific PCIe configuration registers */

#define PCIE_PORT_LINK_CONTROL		0x710

#define PORT_LINK_MODE_MASK		(0x3f << 16)

#define PORT_LINK_MODE_1_LANES		(0x1 << 16)

#define PORT_LINK_MODE_2_LANES		(0x3 << 16)

#define PORT_LINK_MODE_4_LANES		(0x7 << 16)

#define PORT_LINK_MODE_8_LANES		(0xf << 16)



#define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C

#define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)

#define PORT_LOGIC_LINK_WIDTH_MASK	(0x1f << 8)

#define PORT_LOGIC_LINK_WIDTH_1_LANES	(0x1 << 8)

#define PORT_LOGIC_LINK_WIDTH_2_LANES	(0x2 << 8)

#define PORT_LOGIC_LINK_WIDTH_4_LANES	(0x4 << 8)

#define PORT_LOGIC_LINK_WIDTH_8_LANES	(0x8 << 8)



#define PCIE_MSI_ADDR_LO		0x820

#define PCIE_MSI_ADDR_HI		0x824

#define PCIE_MSI_INTR0_ENABLE		0x828

#define PCIE_MSI_INTR0_MASK		0x82C

#define PCIE_MSI_INTR0_STATUS		0x830



#define PCIE_ATU_VIEWPORT		0x900

#define PCIE_ATU_REGION_INBOUND		(0x1 << 31)

#define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)

#define PCIE_ATU_REGION_INDEX2		(0x2 << 0)

#define PCIE_ATU_REGION_INDEX1		(0x1 << 0)

#define PCIE_ATU_REGION_INDEX0		(0x0 << 0)

#define PCIE_ATU_CR1			0x904

#define PCIE_ATU_TYPE_MEM		(0x0 << 0)

#define PCIE_ATU_TYPE_IO		(0x2 << 0)

#define PCIE_ATU_TYPE_CFG0		(0x4 << 0)

#define PCIE_ATU_TYPE_CFG1		(0x5 << 0)

#define PCIE_ATU_CR2			0x908

#define PCIE_ATU_ENABLE			(0x1 << 31)

#define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)

#define PCIE_ATU_LOWER_BASE		0x90C

#define PCIE_ATU_UPPER_BASE		0x910

#define PCIE_ATU_LIMIT			0x914

#define PCIE_ATU_LOWER_TARGET		0x918

#define PCIE_ATU_BUS(x)			(((x) & 0xff) << 24)

#define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)

#define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)

#define PCIE_ATU_UPPER_TARGET		0x91C



/*

 * iATU Unroll-specific register definitions

 * From 4.80 core version the address translation will be made by unroll

 */

#define PCIE_ATU_UNR_REGION_CTRL1	0x00

#define PCIE_ATU_UNR_REGION_CTRL2	0x04

#define PCIE_ATU_UNR_LOWER_BASE		0x08

#define PCIE_ATU_UNR_UPPER_BASE		0x0C

#define PCIE_ATU_UNR_LIMIT		0x10

#define PCIE_ATU_UNR_LOWER_TARGET	0x14

#define PCIE_ATU_UNR_UPPER_TARGET	0x18



/* Register address builder */

#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region)  ((0x3 << 20) | (region << 9))



/* PCIe Port Logic registers */

#define PLR_OFFSET			0x700

#define PCIE_PHY_DEBUG_R1		(PLR_OFFSET + 0x2c)

drivers/pci/dwc/pcie-designware.h

+71 −0
Original line number Diff line number Diff line
@@ -14,6 +14,77 @@ 
#ifndef _PCIE_DESIGNWARE_H

#define _PCIE_DESIGNWARE_H



/* Parameters for the waiting for link up routine */

#define LINK_WAIT_MAX_RETRIES		10

#define LINK_WAIT_USLEEP_MIN		90000

#define LINK_WAIT_USLEEP_MAX		100000



/* Parameters for the waiting for iATU enabled routine */

#define LINK_WAIT_MAX_IATU_RETRIES	5

#define LINK_WAIT_IATU_MIN		9000

#define LINK_WAIT_IATU_MAX		10000



/* Synopsys-specific PCIe configuration registers */

#define PCIE_PORT_LINK_CONTROL		0x710

#define PORT_LINK_MODE_MASK		(0x3f << 16)

#define PORT_LINK_MODE_1_LANES		(0x1 << 16)

#define PORT_LINK_MODE_2_LANES		(0x3 << 16)

#define PORT_LINK_MODE_4_LANES		(0x7 << 16)

#define PORT_LINK_MODE_8_LANES		(0xf << 16)



#define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C

#define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)

#define PORT_LOGIC_LINK_WIDTH_MASK	(0x1f << 8)

#define PORT_LOGIC_LINK_WIDTH_1_LANES	(0x1 << 8)

#define PORT_LOGIC_LINK_WIDTH_2_LANES	(0x2 << 8)

#define PORT_LOGIC_LINK_WIDTH_4_LANES	(0x4 << 8)

#define PORT_LOGIC_LINK_WIDTH_8_LANES	(0x8 << 8)



#define PCIE_MSI_ADDR_LO		0x820

#define PCIE_MSI_ADDR_HI		0x824

#define PCIE_MSI_INTR0_ENABLE		0x828

#define PCIE_MSI_INTR0_MASK		0x82C

#define PCIE_MSI_INTR0_STATUS		0x830



#define PCIE_ATU_VIEWPORT		0x900

#define PCIE_ATU_REGION_INBOUND		(0x1 << 31)

#define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)

#define PCIE_ATU_REGION_INDEX2		(0x2 << 0)

#define PCIE_ATU_REGION_INDEX1		(0x1 << 0)

#define PCIE_ATU_REGION_INDEX0		(0x0 << 0)

#define PCIE_ATU_CR1			0x904

#define PCIE_ATU_TYPE_MEM		(0x0 << 0)

#define PCIE_ATU_TYPE_IO		(0x2 << 0)

#define PCIE_ATU_TYPE_CFG0		(0x4 << 0)

#define PCIE_ATU_TYPE_CFG1		(0x5 << 0)

#define PCIE_ATU_CR2			0x908

#define PCIE_ATU_ENABLE			(0x1 << 31)

#define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)

#define PCIE_ATU_LOWER_BASE		0x90C

#define PCIE_ATU_UPPER_BASE		0x910

#define PCIE_ATU_LIMIT			0x914

#define PCIE_ATU_LOWER_TARGET		0x918

#define PCIE_ATU_BUS(x)			(((x) & 0xff) << 24)

#define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)

#define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)

#define PCIE_ATU_UPPER_TARGET		0x91C



/*

 * iATU Unroll-specific register definitions

 * From 4.80 core version the address translation will be made by unroll

 */

#define PCIE_ATU_UNR_REGION_CTRL1	0x00

#define PCIE_ATU_UNR_REGION_CTRL2	0x04

#define PCIE_ATU_UNR_LOWER_BASE		0x08

#define PCIE_ATU_UNR_UPPER_BASE		0x0C

#define PCIE_ATU_UNR_LIMIT		0x10

#define PCIE_ATU_UNR_LOWER_TARGET	0x14

#define PCIE_ATU_UNR_UPPER_TARGET	0x18



/* Register address builder */

#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region)	\

			((0x3 << 20) | ((region) << 9))



/*

 * Maximum number of MSI IRQs can be 256 per controller. But keep

 * it 32 as of now. Probably we will never need more than 32. If needed,