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Commit b5f80323 authored by Jagadeesh Kona's avatar Jagadeesh Kona Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Update clock and GDSC nodes for KHAJE 

Update the clock controller and GDSC nodes on KHAJE
and add support for usb3_phy_wrapper_gcc_usb30_pipe_clk.

Change-Id: I9034e3984bb735ed902803386e4edc729340217f
parent 1385907c

qcom/khaje-usb.dtsi

+1 −1
Original line number Diff line number Diff line 
#include <dt-bindings/clock/qcom,gcc-bengal.h>

#include <dt-bindings/clock/qcom,gcc-khaje.h>

#include <dt-bindings/msm/msm-bus-ids.h>

&soc {

	/* Primary USB port related controller */

qcom/khaje.dtsi

+20 −13
Original line number Diff line number Diff line 
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/clock/qcom,dispcc-bengal.h>

#include <dt-bindings/clock/qcom,gcc-bengal.h>

#include <dt-bindings/clock/qcom,gpucc-bengal.h>

#include <dt-bindings/clock/qcom,dispcc-khaje.h>

#include <dt-bindings/clock/qcom,gcc-khaje.h>

#include <dt-bindings/clock/qcom,gpucc-khaje.h>

#include <dt-bindings/spmi/spmi.h>

#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>

#include <dt-bindings/msm/msm-bus-ids.h>
@@ -1628,9 +1628,16 @@ 
			clock-output-names = "sleep_clk";

			#clock-cells = <0>;

		};



		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {

			compatible = "fixed-clock";

			clock-frequency = <1000>;

			clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";

			#clock-cells = <0>;

		};

	};



	rpmcc: qcom,rpmcc {

	rpmcc: clock-controller {

		compatible = "qcom,rpmcc-bengal";

		#clock-cells = <1>;

	};
@@ -1644,19 +1651,18 @@ 
		qcom,vm-nav-path;

	};



	gcc: qcom,gcc@1400000 {

		compatible = "qcom,bengal-gcc", "syscon";

	gcc: clock-controller@1400000 {

		compatible = "qcom,khaje-gcc", "syscon";

		reg = <0x1400000 0x1f0000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	dispcc: qcom,dispcc@5f00000 {

		compatible = "qcom,bengal-dispcc", "syscon";

	dispcc: clock-controller@5f00000 {

		compatible = "qcom,khaje-dispcc", "syscon";

		reg = <0x05f00000 0x20000>;

		reg-names = "cc_base";

		clock-names = "cfg_ahb_clk";
@@ -1666,8 +1672,8 @@ 
		#reset-cells = <1>;

	};



	gpucc: qcom,gpucc@5990000 {

		compatible = "qcom,bengal-gpucc", "syscon";

	gpucc: clock-controller@5990000 {

		compatible = "qcom,khaje-gpucc", "syscon";

		reg = <0x5990000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;
@@ -1687,8 +1693,8 @@ 
		reg = <0xf11101c 0x4>;

	};



	debugcc: qcom,cc-debug {

		compatible = "qcom,bengal-debugcc";

	debugcc: clock-controller@0 {

		compatible = "qcom,khaje-debugcc";

		qcom,gcc = <&gcc>;

		qcom,dispcc = <&dispcc>;

		qcom,gpucc = <&gpucc>;
@@ -2947,6 +2953,7 @@ tpdm_turing_llm: tpdm@8861000 { 
};



&mdss_core_gdsc {

	reg = <0x5f01004 0x4>;

	qcom,support-hw-trigger;

	status = "ok";

};